kern/amd64: Add model specific register helpers

Signed-off-by: Ian Moffett <ian@osmora.org>

1 files changed, 70 insertions, 0 deletions

diff --git a/sys/inc/arch/amd64/msr.h b/sys/inc/arch/amd64/msr.h
new file mode 100644
index 0000000..ab0deb9
--- /dev/null
+++ b/sys/inc/arch/amd64/msr.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2025 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPKERNE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LKERNS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * PKERNSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MACHINE_MSR_H_
+#define _MACHINE_MSR_H_ 1
+
+#include <sys/cdefs.h>
+#include <sys/types.h>
+
+#define IA32_GS_BASE        0xC0000101
+#define IA32_KERNEL_GS_BASE 0xC0000102
+
+__always_inline static inline uint64_t
+rdmsr(uint32_t msr)
+{
+    uint32_t lo, hi;
+
+    __asm(
+        "rdmsr"
+        : "=a" (lo), "=d" (hi)
+        : "c" (msr)
+        : "memory"
+    );
+
+    return ((uint64_t)hi << 32) | lo;
+}
+
+__always_inline static inline void
+wrmsr(uint32_t msr, uint64_t val)
+{
+    uint32_t lo, hi;
+
+    lo = val & 0xFFFFFFFF;
+    hi = (val >> 32) & 0xFFFFFFFF;
+
+    __asm(
+        "wrmsr"
+        :
+        : "c" (msr), "a" (lo), "d" (hi)
+        : "memory"
+    );
+}
+
+#endif  /* !_MACHINE_MSR_H_ */