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authorIan Moffett <ian@osmora.org>2024-08-06 21:39:10 -0400
committerIan Moffett <ian@osmora.org>2024-08-07 10:29:27 -0400
commited53f9368ee8258ea0b2c803e8a641daa1183042 (patch)
treea05bc14743e1cb458b55079e11d740f4c0a2c191 /sv/soc/bus
parent9d500066b9d25617c8bfae770d27b85a8b745269 (diff)
soc: bus: Fix DMA channel 2 and 3 MMIO basemain
Signed-off-by: Ian Moffett <ian@osmora.org>
Diffstat (limited to 'sv/soc/bus')
-rw-r--r--sv/soc/bus/dmactl.sv4
1 files changed, 2 insertions, 2 deletions
diff --git a/sv/soc/bus/dmactl.sv b/sv/soc/bus/dmactl.sv
index c0851c1..fc6ade6 100644
--- a/sv/soc/bus/dmactl.sv
+++ b/sv/soc/bus/dmactl.sv
@@ -36,8 +36,8 @@ module dmactl #(
/* MMIO bases for DMA channels */
parameter C0_MMIO_BASE = 48'h1000140,
parameter C1_MMIO_BASE = 48'h1000153,
- parameter C2_MMIO_BASE = 48'h1000153,
- parameter C3_MMIO_BASE = 48'h1000166,
+ parameter C2_MMIO_BASE = 48'h1000166,
+ parameter C3_MMIO_BASE = 48'h100016E,
/* Channel control bits */
parameter CCTL_START = 0,