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Diffstat (limited to 'src/sys/arch/amd64/cpu/cpu_conf.c')
-rw-r--r--src/sys/arch/amd64/cpu/cpu_conf.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/sys/arch/amd64/cpu/cpu_conf.c b/src/sys/arch/amd64/cpu/cpu_conf.c
index 9399973..de0e9bc 100644
--- a/src/sys/arch/amd64/cpu/cpu_conf.c
+++ b/src/sys/arch/amd64/cpu/cpu_conf.c
@@ -30,11 +30,35 @@
#include <sys/cpuvar.h>
#include <machine/boot.h>
#include <machine/msr.h>
+#include <machine/idt.h>
+#include <machine/trap.h>
+
+/*
+ * Initialize interrupt vectors
+ */
+static void
+init_vectors(void)
+{
+ idt_set_desc(0x0, IDT_TRAP_GATE, ISR(arith_err), 0);
+ idt_set_desc(0x2, IDT_TRAP_GATE, ISR(nmi), 0);
+ idt_set_desc(0x3, IDT_TRAP_GATE, ISR(breakpoint_handler), 0);
+ idt_set_desc(0x4, IDT_TRAP_GATE, ISR(overflow), 0);
+ idt_set_desc(0x5, IDT_TRAP_GATE, ISR(bound_range), 0);
+ idt_set_desc(0x6, IDT_TRAP_GATE, ISR(invl_op), 0);
+ idt_set_desc(0x8, IDT_TRAP_GATE, ISR(double_fault), 0);
+ idt_set_desc(0xA, IDT_TRAP_GATE, ISR(invl_tss), 0);
+ idt_set_desc(0xB, IDT_TRAP_GATE, ISR(segnp), 0);
+ idt_set_desc(0xC, IDT_TRAP_GATE, ISR(ss_fault), 0);
+ idt_set_desc(0xD, IDT_TRAP_GATE, ISR(general_prot), 0);
+ idt_set_desc(0xE, IDT_TRAP_GATE, ISR(page_fault), 0);
+}
void
cpu_conf(struct pcore *pcore)
{
pcore->self = pcore;
+ init_vectors();
+ idt_load();
platform_boot();
/* We use %GS to store the processor */