kern/amd64: mmu: Add page-level cacheability attrs

This commit adds support for page-level cacheability attributes. We have
added the pmap_set_cache() as well as some MMU_CACHE_* bits

Signed-off-by: Ian Moffett <ian@osmora.org>

1 files changed, 23 insertions, 0 deletions

diff --git a/src/sys/include/vm/mmu.h b/src/sys/include/vm/mmu.h
index be0678e..54a694b 100644
--- a/src/sys/include/vm/mmu.h
+++ b/src/sys/include/vm/mmu.h
@@ -41,6 +41,17 @@
 #include <machine/vas.h>    /* standard */
 #include <vm/vm.h>
 
+/* Caching types */
+#define MMU_CACHE_UC BIT(0) /* Uncachable */
+#define MMU_CACHE_WT BIT(1) /* Write-through */
+#define MMU_CACHE_GL BIT(2) /* Global (if supported) */
+
+/*
+ * Represents caching attributes that can be applied
+ * to the address space (see VM_CACHE_* above).
+ */
+typedef uint16_t cacheattr_t;
+
 /*
  * Standard memory protection flags
  */
@@ -127,4 +138,16 @@ int mmu_write_vas(struct vm_vas *vas);
  */
 int mmu_free_vas(struct vm_vas *vas);
 
+/*
+ * Update page-level caching attributes
+ *
+ * @vas: Virtual address space to target
+ * @va: Virtual page base to update
+ * @attr: Attributes to set
+ *
+ * Returns zero on success, otherwise a less than
+ * zero value to indicate error.
+ */
+int pmap_set_cache(struct vm_vas *vas, vaddr_t va, cacheattr_t attr);
+
 #endif  /* !_MACHINE_MMU_H_ */