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authorsigsegv7 <ian@osmora.org>2023-11-12 00:16:24 -0500
committersigsegv7 <ian@osmora.org>2023-11-12 00:16:24 -0500
commitf53ac3212fe8f07c99aef348e754aa8ab00081dc (patch)
tree4f3c5ab942e900bb11e8cce4825061946d278b44 /sys/arch
parentc4c3d0e5479f0415fcc21eeedcecfe745ee17dc4 (diff)
kernel/amd64: lapic: Remove ESR support
ESR support should be added later on; there is no need for it as of now... Signed-off-by: sigsegv7 <ian@osmora.org>
Diffstat (limited to 'sys/arch')
-rw-r--r--sys/arch/amd64/lapic.c21
1 files changed, 0 insertions, 21 deletions
diff --git a/sys/arch/amd64/lapic.c b/sys/arch/amd64/lapic.c
index 6f2f6c1..af219d2 100644
--- a/sys/arch/amd64/lapic.c
+++ b/sys/arch/amd64/lapic.c
@@ -208,27 +208,6 @@ lapic_set_ldr(void)
lapic_writel(LAPIC_LDR, LAPIC_STARTUP_LID);
}
-/*
- * Reads the Local APIC error status
- * register. Returns the value read.
- *
- * XXX: It is a good idea to save the value returned as
- * each read will clear the register.
- */
-static inline uint32_t
-lapic_read_esr(void)
-{
- /*
- * We'll need to write 0 to clear the ESR and reload
- * it with any new errors that happened... In xAPIC mode
- * we can write anything to do this; however, in x2APIC
- * mode, writes of 0 are enforced. We'll only write 0 to
- * work both with x2APIC and xAPIC mode...
- */
- lapic_writel(LAPIC_ERR, 0);
- return lapic_readl(LAPIC_ERR);
-}
-
void
lapic_timer_init(size_t *freq_out)
{