From 6ed636b8efe4d50ab013cf337ad634513eddbb6d Mon Sep 17 00:00:00 2001
From: Ian Moffett <ian@osmora.org>
Date: Tue, 18 Nov 2025 01:02:27 -0500
Subject: kern/amd64: Do low-level processor configuration

This commit seperates low-level processor configuration into the
cpu_loinit() function. This is to be called for the BSP and per AP.

Signed-off-by: Ian Moffett <ian@osmora.org>
---
 sys/arch/amd64/cpu/boot.S | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

(limited to 'sys/arch/amd64/cpu/boot.S')

diff --git a/sys/arch/amd64/cpu/boot.S b/sys/arch/amd64/cpu/boot.S
index 0cda6a7..737092f 100644
--- a/sys/arch/amd64/cpu/boot.S
+++ b/sys/arch/amd64/cpu/boot.S
@@ -27,6 +27,8 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <md/msr.h>
+
     .text
     .globl _start
     .extern uart_init
@@ -44,6 +46,7 @@ _start:
     lea GDTR(%rip), %rdi    /* Our GDTR */
     call gdt_load           /* Load our GDT */
     call idt_load           /* Load our IDT */
+    call cpu_loinit         /* Initialize processor state */
 
     /*
      * RV7 will default to APIC operation, as per a section
@@ -62,6 +65,31 @@ _start:
     hlt
     jmp 1b
 
+    .globl cpu_loinit
+cpu_loinit:
+    /*
+     * Initialize low-level CPU state
+     */
+    push %r12
+    push %r13
+    push %r14
+    push %r15
+    push %rbx
+    push %rbp
+
+    mov $IA32_EFER, %ecx    /* IA32_EFER */
+    rdmsr                   /* -> EAX */
+    or $1<<11, %eax         /* EFER.NXE */
+    wrmsr                   /* Write it back */
+
+    pop %rbp
+    pop %rbx
+    pop %r15
+    pop %r14
+    pop %r13
+    pop %r12
+    retq
+
     .section .rodata
 bootmsg:
     .ascii "[ preparing since 2025 ]\n"
-- 
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