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2024-02-16Add AVX supportIan Moffett
Signed-off-by: Ian Moffett <ian@osmora.org>
2024-02-16sse_accel.h -> accel.hIan Moffett
Signed-off-by: Ian Moffett <ian@osmora.org>
2024-02-16Remove redundant shiftIan Moffett
Signed-off-by: Ian Moffett <ian@osmora.org>
2024-02-16Update copyrightIan Moffett
Signed-off-by: Ian Moffett <ian@osmora.org>
2023-10-20Ensure cpuid macro is only defined on AMD64sigsegv7
Signed-off-by: sigsegv7 <ian@vegaa.systems>
2023-09-18cleanup commentssigsegv7
Signed-off-by: sigsegv7 <ian@vegaa.systems>
2023-09-18Add additional information to commentsigsegv7
Signed-off-by: sigsegv7 <ian@vegaa.systems>
2023-09-18cleanup formattingsigsegv7
Signed-off-by: sigsegv7 <ian@vegaa.systems>
2023-09-18Fix register mismatchsigsegv7
Signed-off-by: sigsegv7 <ian@vegaa.systems>
2023-09-18Fix overflow issue + odd behavioursigsegv7
It is best to check for an overflow risk and lower the step BEFORE we actually perform the inversion Signed-off-by: sigsegv7 <ian@vegaa.systems>
2023-09-18Shift step left by 1 if SSE is supportedsigsegv7
This is a faster way of increasing the step as they are in powers of two. Signed-off-by: sigsegv7 <ian@vegaa.systems>
2023-09-18Optimize with SSE2/SSE3 and 128 bit inversionssigsegv7
Signed-off-by: sigsegv7 <ian@vegaa.systems>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-22 21:04:31 +0000