From 04c59c82632e7c6cf45b5fb952364ff39835d513 Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Sat, 3 Aug 2024 14:38:54 -0400 Subject: soc: pimc: Update PIMC IRQACK timing requirements Signed-off-by: Ian Moffett --- sv/soc/irq/irqchip.md | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'sv/soc') diff --git a/sv/soc/irq/irqchip.md b/sv/soc/irq/irqchip.md index 5faf090..9e9b595 100644 --- a/sv/soc/irq/irqchip.md +++ b/sv/soc/irq/irqchip.md @@ -25,8 +25,7 @@ each connected to their respective IRQ lines. During system startup, LINENO[7:0] and NOTIFY# will be in an undefined state. Stage 1 firmware is responsible for initializing the PIMC before it is ready for operation. The PIMC is initialized -by pulsing IRQACK high for exactly one clock cycle. It is recommended that IRQACK should be left high -for at least 2 ms. +by pulsing IRQACK high for at least 2 ms. As soon as a rising edge of the PIMC CLK signal occurs with IRQACK pulled high, NOTIFY# is pulled high and LINENO[7:0] becomes zero. -- cgit v1.2.3