diff options
| -rw-r--r-- | README.md | 112 | ||||
| -rw-r--r-- | sv/soc/bus/dmactl.sv | 8 | ||||
| -rw-r--r-- | sv/soc/irq/pimc.sv | 4 | ||||
| -rw-r--r-- | tb/soc/irq/tb_pimc.cpp | 4 |
4 files changed, 109 insertions, 19 deletions
@@ -16,6 +16,21 @@ Registers store data which can be accessed at any time. These include special re | `fp` | 64 bits | Frame pointer | | `ptp` | 64 bits | Page tree pointer | +## Link Registers + +The link registers are for storing specific return addresses from a subroutine + +| Name | Size | Purpose | +| ---------- | -------- | --------------------------- +| `blr` | 64 bits | Branch Link Register | +| `ilr` | 64 bits | Interrupt Link Register | + +When calling a subroutine, it will need to know where to return to +when the execution finishes. To achieve this, we use the branch link +register (BLR). In situations where an interrupt has occurred on the +system, the CPU would need to know where to return to from the interrupt +context, in cases such as this, we'd use the Interrupt Link Register (ILR). + ### Internal Registers Only accessed by the CPU for certain instructions. Cannot be directly read/written. @@ -25,17 +40,69 @@ Only accessed by the CPU for certain instructions. Cannot be directly read/writt | `rp` | 64 bits | Return pointer for branches | | `ins` | 64 bits | Current instruction at `pc` | +## Special Registers + +OSMX64 provides "special" control registers that may vary depending on the chip +revision. These registers typically include chip-specific mode/control bits to +configure the processor for certain modes of operations, etc. These registers +cannot be accessed via the "mov" instruction and instead rely on independent wrs/rrs +(i.e., special register write / special register read) instructions. + +### Common Special Registers + +| Name | Size | Purpose | +| --------- | ------- | --------------------------- | +| `SR_STATE`| 64 bits | Processor state bits | + + +### SR\_STATE + +| Bit | Meaning | Purpose +|------|---------------------- | ---------------------- | +| 0 | Reserved | Must be zero | +| 1 | Supervisor | Supervisor mode enable | +| 2 | Carry | Arithmetic carry flag | +| 3-31 | Reserved (must be 0) | Must be zero | + + +#### Supervisor bit +The supervisor bit may only be writable in a privileged mode of execution +and is therefore readonly in user contexts (writes ignored). It may be unset +by system software to transition the processor into a user context. This bit +may only transition from a 0 to a 1 during an interrupt/trap, therefore manually +writing a 1 to this bit is ignored by the processor. + +#### Carry bit +Indicates whether an arithmetic operation has resulted in a +carry/borrow. + ## Instructions + +### Special Register Access + +Special registers are identified with a 16-bit Special Register ID (SRID) +and can be accessed through two special instructions. + +| Mnemonic | Effect | +| -------------------------------- | ----------------------- | +| `wrs` srid: r/imm, val: r | `SREGS[srid]` = `val` | +| `rrs` dest: r, srid: r/imm | `dest` = `SREGS[srid]` | + + ### Bitwise Instructions Bitwise logic operations can write to all registers except `v0`-`v7`, `x0` and `pc`. Can read from all registers except `v0`-`v7`. -| Mnemonic | Effect | -| -------------------------------- | ---------------------- | -| `and` dst: r, reg: r, val: r/imm | `dst` = `dst` & `val` | -| `or` dst: r, reg: r, val: r/imm | `dst` = `dst` \| `val` | -| `xor` dst: r, reg: r, val: r/imm | `dst` = `dst` ^ `val` | +| Mnemonic | Effect | +| -------------------------------- | ------------------------------- | +| `and` dst: r, reg: r, val: r/imm | `dst` = `dst` & `val` | +| `or` dst: r, reg: r, val: r/imm | `dst` = `dst` \| `val` | +| `xor` dst: r, reg: r, val: r/imm | `dst` = `dst` ^ `val` | +| `mrob` dst: r: mask [bit]: imm | Fill byte of 'dst' with 'mask' | +| `mrow` dst: r: mask [bit]: imm | Fill word of 'dst' with 'mask' | +| `mrod` dst: r: mask [bit]: imm | Fill dword of 'dst' with 'mask' | +| `mroq` dst: r: mask [bit]: imm | Fill qword of 'dst' with 'mask' | #### Example ``` @@ -82,10 +149,10 @@ Arithmetic operations can write to all registers except `v0`-`v7`, `x0` and `pc` | Mnemonic | Effect | | ------------------------------------ | --------------------- | -| `add` dst: r, reg: r, val: r/imm | `dst` = `dst` + `val` | -| `sub` dst: r, reg: r, val: r/imm | `dst` = `dst` - `val` | -| `mul` dst: r, reg: r, val: r/imm | `dst` = `dst` * `val` | -| `div` dst: r, reg: r, val: r/imm | `dst` = `dst` / `val` | +| `add` dst: r, val: r/imm | `dst` = `dst` + `val` | +| `sub` dst: r, val: r/imm | `dst` = `dst` - `val` | +| `mul` dst: r, val: r/imm | `dst` = `dst` * `val` | +| `div` dst: r, val: r/imm | `dst` = `dst` / `val` | | `inc` dst: r | `dst` = `dst` + `1` | | `dec` dst: r | `dst` = `dst` - `1` | @@ -105,8 +172,8 @@ Control flow instructions are used to control which instructions the CPU execute | Mnemonic | Effect | | -------------------------------------- | ----------------------------------------------- | | `hlt` | Execution halted | -| `br` dst: r/m/imm | `pc` = `dst` | -| `brl` dst: r/m/imm | `rp` = `pc` + size of opcode, then `pc` = `dst` | +| `br` dst: r | `pc` = `dst` | +| `brl` dst: r | `rp` = `pc` + size of opcode, then `pc` = `dst` | | `bret` | `pc` = `rp` | | `beq` a: r/m, b: r/m/imm, dst: r/m/imm | Iff `a` = `b`, `pc` = `dst` | | `bne` a: r/m, b: r/m/imm, dst: r/m/imm | Iff `a` != `b`, `pc` = `dst` | @@ -127,5 +194,28 @@ mov x1, #3 /* Iff x1 - x1 != 0, x1 equals 2 */ ``` +### Opcode list + +- `NOP`: `0x00` +- `ADD`: `0x01` +- `SUB`: `0x02` +- `MUL`: `0x03` +- `DIV`: `0x04` +- `INC`: `0x05` +- `DEC`: `0x06` +- `OR`: `0x07` +- `XOR`: `0x08` +- `AND`: `0x09` +- `NOT`: `0x0A` +- `SLL`: `0x0B` +- `SRL`: `0x0C` +- `MOV_IMM`: `0x0D` +- `HLT`: `0x0E` +- `BR`: `0x0F` +- `MROB`: `0x10` +- `MROW`: `0x11` +- `MROD`: `0x12` +- `MROQ`: `0x13` + Copyright (c) 2024 Quinn Stephens and Ian Marco Moffett. All rights reserved. diff --git a/sv/soc/bus/dmactl.sv b/sv/soc/bus/dmactl.sv index c0851c1..27a13ec 100644 --- a/sv/soc/bus/dmactl.sv +++ b/sv/soc/bus/dmactl.sv @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Athena Systems LLC and Ian Marco Moffett + * Copyright (c) 2024-2025 Ian Marco Moffett and the Osmora Team. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -10,7 +10,7 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its + * 3. Neither the name of Hyra nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * @@ -36,8 +36,8 @@ module dmactl #( /* MMIO bases for DMA channels */ parameter C0_MMIO_BASE = 48'h1000140, parameter C1_MMIO_BASE = 48'h1000153, - parameter C2_MMIO_BASE = 48'h1000153, - parameter C3_MMIO_BASE = 48'h1000166, + parameter C2_MMIO_BASE = 48'h1000166, + parameter C3_MMIO_BASE = 48'h100016E, /* Channel control bits */ parameter CCTL_START = 0, diff --git a/sv/soc/irq/pimc.sv b/sv/soc/irq/pimc.sv index 15b82c9..21d5dde 100644 --- a/sv/soc/irq/pimc.sv +++ b/sv/soc/irq/pimc.sv @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Athena Systems LLC and Ian Marco Moffett + * Copyright (c) 2024-2025 Ian Marco Moffett and the Osmora Team. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -10,7 +10,7 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its + * 3. Neither the name of Hyra nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * diff --git a/tb/soc/irq/tb_pimc.cpp b/tb/soc/irq/tb_pimc.cpp index ec06a5d..7365649 100644 --- a/tb/soc/irq/tb_pimc.cpp +++ b/tb/soc/irq/tb_pimc.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Athena Systems LLC and Ian Marco Moffett + * Copyright (c) 2024-2025 Ian Marco Moffett and the Osmora Team. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -10,7 +10,7 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its + * 3. Neither the name of Hyra nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * |