soc: pimc: Document MMIO interface

Signed-off-by: Ian Moffett <ian@osmora.org>

2 files changed, 37 insertions, 0 deletions

diff --git a/sv/soc/irq/images/irqmask.png b/sv/soc/irq/images/irqmask.png
new file mode 100644
index 0000000..2feddb2
--- /dev/null
+++ b/sv/soc/irq/images/irqmask.png
diff --git a/sv/soc/irq/irqchip.md b/sv/soc/irq/irqchip.md
index e4705a7..d011e15 100644
--- a/sv/soc/irq/irqchip.md
+++ b/sv/soc/irq/irqchip.md
@@ -11,6 +11,11 @@ each connected to their respective IRQ lines.
 | IRQACK      | Interrupt acknowledgement   |
 | LINENO[7:0] | IRQ line to be serviced     |
 | NOTIFY#     | Signals an active IRQ       |
+| MMIO_ADDR   | MMIO r/w address            |
+| MMIO_RE     | MMIO read enable            |
+| MMIO_WE     | MMIO write enable           |
+| MMIO_WDATA  | MMIO write data             |
+| MMIO_RDATA  | MMIO read data              |
 | CLK         | PIMC Clock                  |
 
 ## PIMC Startup State
@@ -38,3 +43,35 @@ it can be acknowledged by pulsing IRQACK high for 2 ms. After an IRQ has been ac
 is pulled high and LINENO[7:0] is cleared to zero.
 
 ![signals](images/irq.png)
+
+## MMIO Interface
+
+Some registers within the PIMC chip are memory mapped and can be accessed through the MMIO interface. For example,
+the IRQ table is accessed through physical address 0x1000 + OFFSET.
+
+### MMIO Interface Semantics
+
+The MMIO_ADDR input from mainbus is set to the address being accessed. The MMIO_RE (Read Enable) and
+MMIO_WE (Write Enable) signals are used for read/write operations and are mutually exclusive. As soon as one
+of these signals are pulled high, data transfer begins.
+
+- Pulse MMIO_RE high to read data onto MMIO_RDATA.
+- Pulse MMIO_WE high to write data from MMIO_WDATA.
+
+![masking](images/irqmask.png)
+
+### MMIO Interface Registers
+
+#### IRQ Table
+
+The IRQ table is a set of registers that manage where and how IRQs get directed.
+The IRQ line number acts as the index into this table.
+
+| Bits        | Field         |
+| ----------- | ------------- |
+| 7:0         | Processor ID  |
+| 8           | Line mask     |
+| 31:9        | Reserved      |
+
+The Processor ID field contains the ID of the processor for this IRQ to be directed to.
+If the Line Mask bit is set to 1, the PIMC chip will ignore interrupts from this line.