From 39bd29f7dea6426db6fa78b4f18aae9aa76d8bc4 Mon Sep 17 00:00:00 2001
From: Ian Moffett <ian@osmora.org>
Date: Fri, 3 Oct 2025 16:36:06 -0400
Subject: np: piir: Add bitmap based register allocation

Introduce register allocation via a bitmap where each bit corresponds to
a specific register index.

Signed-off-by: Ian Moffett <ian@osmora.org>
---
 src/sys/arch/amd64/np/piir_conv.c | 46 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 45 insertions(+), 1 deletion(-)

(limited to 'src/sys/arch/amd64/np/piir_conv.c')

diff --git a/src/sys/arch/amd64/np/piir_conv.c b/src/sys/arch/amd64/np/piir_conv.c
index 280e0a7..f949f48 100644
--- a/src/sys/arch/amd64/np/piir_conv.c
+++ b/src/sys/arch/amd64/np/piir_conv.c
@@ -55,9 +55,25 @@ typedef enum {
     R32_ESP,
     R32_EBP,
     R32_ESI,
-    R32_RDI
+    R32_RDI,
+    __R32_MAX
 } r32_t;
 
+/*
+ * Valid 64-bit register IDs
+ */
+typedef enum {
+    R64_RAX,
+    R64_RCX,
+    R64_RDX,
+    R64_RBX,
+    R64_RSP,
+    R64_RBP,
+    R64_RSI,
+    R64_RDI,
+    __R64_MAX
+} r64_t;
+
 /* SYS-V ABI specific */
 #define R32_RETVAL R32_EAX
 
@@ -128,3 +144,31 @@ md_piir_decode(struct np_work *work, struct piir_vm *vm, ir_byte_t input)
     }
     return 0;
 }
+
+reg_t
+md_alloc_reg(struct np_work *work, struct piir_vm *vm, int flags)
+{
+    if (work == NULL || vm == NULL) {
+        return -EINVAL;
+    }
+
+    /* If a bit is unset, it is free */
+    for (int i = 0; i < __R32_MAX; ++i) {
+        if (!ISSET(vm->regset, BIT(i))) {
+            vm->regset |= BIT(i);
+            return i;
+        }
+    }
+
+    return -1;
+}
+
+void
+md_free_reg(struct np_work *work, struct piir_vm *vm, reg_t reg)
+{
+    if (work == NULL || vm == NULL) {
+        return;
+    }
+
+    vm->regset &= ~BIT(reg);
+}
-- 
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