From 51aca35fe3cf86fc9652a20a3e6ae23553f27665 Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Mon, 15 Sep 2025 07:24:05 -0400 Subject: kern/amd64: Add exception handlers Signed-off-by: Ian Moffett --- src/sys/arch/amd64/cpu/cpu_conf.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'src/sys/arch/amd64/cpu/cpu_conf.c') diff --git a/src/sys/arch/amd64/cpu/cpu_conf.c b/src/sys/arch/amd64/cpu/cpu_conf.c index 9399973..de0e9bc 100644 --- a/src/sys/arch/amd64/cpu/cpu_conf.c +++ b/src/sys/arch/amd64/cpu/cpu_conf.c @@ -30,11 +30,35 @@ #include #include #include +#include +#include + +/* + * Initialize interrupt vectors + */ +static void +init_vectors(void) +{ + idt_set_desc(0x0, IDT_TRAP_GATE, ISR(arith_err), 0); + idt_set_desc(0x2, IDT_TRAP_GATE, ISR(nmi), 0); + idt_set_desc(0x3, IDT_TRAP_GATE, ISR(breakpoint_handler), 0); + idt_set_desc(0x4, IDT_TRAP_GATE, ISR(overflow), 0); + idt_set_desc(0x5, IDT_TRAP_GATE, ISR(bound_range), 0); + idt_set_desc(0x6, IDT_TRAP_GATE, ISR(invl_op), 0); + idt_set_desc(0x8, IDT_TRAP_GATE, ISR(double_fault), 0); + idt_set_desc(0xA, IDT_TRAP_GATE, ISR(invl_tss), 0); + idt_set_desc(0xB, IDT_TRAP_GATE, ISR(segnp), 0); + idt_set_desc(0xC, IDT_TRAP_GATE, ISR(ss_fault), 0); + idt_set_desc(0xD, IDT_TRAP_GATE, ISR(general_prot), 0); + idt_set_desc(0xE, IDT_TRAP_GATE, ISR(page_fault), 0); +} void cpu_conf(struct pcore *pcore) { pcore->self = pcore; + init_vectors(); + idt_load(); platform_boot(); /* We use %GS to store the processor */ -- cgit v1.2.3