From 7a38e4f8aac5cfe7a4503589a2cf8b953295e04b Mon Sep 17 00:00:00 2001
From: Ian Moffett <ian@osmora.org>
Date: Tue, 22 Jul 2025 15:26:46 -0400
Subject: oemu: cpu: Decode the BR instruction

Add support for interpreting the BR (branch) instruction. This
instruction takes in a single register operand containing an address to
reassign the instruction pointer to.

Signed-off-by: Ian Moffett <ian@osmora.org>
---
 usr.bin/oemu/cpu.c                 | 30 ++++++++++++++++++++++++++++++
 usr.bin/oemu/include/oemu/osmx64.h |  1 +
 2 files changed, 31 insertions(+)

(limited to 'usr.bin/oemu')

diff --git a/usr.bin/oemu/cpu.c b/usr.bin/oemu/cpu.c
index 418febb..07ddc7b 100644
--- a/usr.bin/oemu/cpu.c
+++ b/usr.bin/oemu/cpu.c
@@ -197,6 +197,33 @@ cpu_div(struct oemu_cpu *cpu, inst_t *inst)
         imm, inst->imm, inst->rd, regs->xreg[inst->rd]);
 }
 
+/*
+ * Decode the INST_DIV instruction
+ */
+static void
+cpu_br(struct oemu_cpu *cpu, inst_t *inst)
+{
+    struct cpu_regs *regs = &cpu->regs;
+    imm_t imm;
+    addr_t br_to;
+
+    if (inst->rd > NELEM(regs->xreg)) {
+        printf("bad register operand for 'br'\n");
+        return;
+    }
+
+    /*
+     * If we are branching to the reset vector, might
+     * as well reset all state.
+     */
+    br_to = regs->xreg[inst->rd];
+    if (br_to == 0) {
+        cpu_reset(cpu);
+    }
+
+    regs->ip = br_to;
+}
+
 /*
  * Reset a CPU to a default state
  */
@@ -280,6 +307,9 @@ cpu_kick(struct oemu_cpu *cpu, struct sysmem *mem)
         case INST_DIV:
             cpu_div(cpu, inst);
             break;
+        case INST_BR:
+            cpu_br(cpu, inst);
+            break;
         }
 
         /* Is this a halt instruction? */
diff --git a/usr.bin/oemu/include/oemu/osmx64.h b/usr.bin/oemu/include/oemu/osmx64.h
index e9baae0..b1df5d3 100644
--- a/usr.bin/oemu/include/oemu/osmx64.h
+++ b/usr.bin/oemu/include/oemu/osmx64.h
@@ -48,6 +48,7 @@
 #define INST_SRL      0x12    /* Shift right logical operation */
 #define INST_MOV_IMM  0x13    /* Data move operation from IMM */
 #define INST_HLT      0x14    /* Halt */
+#define INST_BR       0x15    /* Branch */
 
 /* Registers */
 #define REG_X0   0x00
-- 
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