From e4a2de4bee8e24b85291441b8291ba59048d4212 Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Mon, 9 Jun 2025 23:50:23 -0400 Subject: kernel/amd64: Flush TLB per cache attr update - Use pmap_update_tbl() to ensure that the TLB is flushed when caching attributes are updated. Signed-off-by: Ian Moffett --- sys/arch/amd64/amd64/pmap.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'sys') diff --git a/sys/arch/amd64/amd64/pmap.c b/sys/arch/amd64/amd64/pmap.c index 5b0d046..8193838 100644 --- a/sys/arch/amd64/amd64/pmap.c +++ b/sys/arch/amd64/amd64/pmap.c @@ -282,6 +282,8 @@ int pmap_set_cache(struct vas vas, vaddr_t va, int type) { uintptr_t *tbl; + uint32_t flags; + paddr_t pa; int status; size_t idx; @@ -289,22 +291,24 @@ pmap_set_cache(struct vas vas, vaddr_t va, int type) return status; idx = pmap_get_level_index(1, va); + pa = tbl[idx] & PTE_ADDR_MASK; + flags = tbl[idx] & ~PTE_ADDR_MASK; /* Set the caching policy */ switch (type) { case VM_CACHE_UC: - tbl[idx] |= PTE_PCD; - tbl[idx] &= ~PTE_PWT; + flags |= PTE_PCD; + flags &= ~PTE_PWT; break; case VM_CACHE_WT: - tbl[idx] &= ~PTE_PCD; - tbl[idx] |= PTE_PWT; + flags &= ~PTE_PCD; + flags |= PTE_PWT; break; default: return -EINVAL; } - return 0; + return pmap_update_tbl(vas, va, (pa | flags), false); } bool -- cgit v1.2.3