From 30495d6f06108864c151e744ec1aad98e70c3334 Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Mon, 11 Dec 2023 22:46:45 -0500 Subject: kernel/amd64: Add Task State Segment Signed-off-by: Ian Moffett --- sys/arch/amd64/gdt.c | 5 ++ sys/arch/amd64/machdep.c | 19 ++++++++ sys/arch/amd64/tss.S | 41 +++++++++++++++++ sys/arch/amd64/tss.c | 82 +++++++++++++++++++++++++++++++++ sys/include/arch/amd64/cpu.h | 2 + sys/include/arch/amd64/gdt.h | 1 + sys/include/arch/amd64/tss.h | 106 +++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 256 insertions(+) create mode 100644 sys/arch/amd64/tss.S create mode 100644 sys/arch/amd64/tss.c create mode 100644 sys/include/arch/amd64/tss.h (limited to 'sys') diff --git a/sys/arch/amd64/gdt.c b/sys/arch/amd64/gdt.c index 209e2f7..667170a 100644 --- a/sys/arch/amd64/gdt.c +++ b/sys/arch/amd64/gdt.c @@ -72,8 +72,13 @@ struct gdt_entry g_gdt[256] = { .granularity = 0x00, .base_hi = 0x00 }, + + /* TSS segment (0x28) */ + {0} }; +struct gdt_entry *g_gdt_tss = &g_gdt[GDT_TSS]; + struct gdtr g_gdtr = { .limit = sizeof(struct gdt_entry) * 256 - 1, .offset = (uintptr_t)&g_gdt[0] diff --git a/sys/arch/amd64/machdep.c b/sys/arch/amd64/machdep.c index 3f3feb0..a466d38 100644 --- a/sys/arch/amd64/machdep.c +++ b/sys/arch/amd64/machdep.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include @@ -44,6 +45,16 @@ __KERNEL_META("$Hyra$: machdep.c, Ian Marco Moffett, " #define ISR(func) ((uintptr_t)func) #define INIT_FLAG_IOAPIC 0x00000001U +static inline void +init_tss(struct cpu_info *cur_cpu) +{ + struct tss_desc *desc; + + desc = (struct tss_desc *)g_gdt_tss; + write_tss(cur_cpu, desc); + tss_load(); +} + static void interrupts_init(void) { @@ -73,6 +84,8 @@ processor_init(void) /* Indicates what doesn't need to be init anymore */ static uint8_t init_flags = 0; + struct cpu_info *cur_cpu = NULL; + interrupts_init(); gdt_load(&g_gdtr); @@ -82,6 +95,12 @@ processor_init(void) } lapic_init(); /* Per core */ + cur_cpu = this_cpu(); + + CPU_INFO_LOCK(cur_cpu); + cur_cpu->tss = NULL; + init_tss(cur_cpu); + CPU_INFO_UNLOCK(cur_cpu); /* Enable spectre mitigation if enabled */ if (try_spectre_mitigate != NULL) diff --git a/sys/arch/amd64/tss.S b/sys/arch/amd64/tss.S new file mode 100644 index 0000000..be44a04 --- /dev/null +++ b/sys/arch/amd64/tss.S @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2023 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +__KERNEL_META "$Hyra$: tss.S, Ian Marco Moffett, \ + Low level TSS code" + +.globl tss_load +tss_load: + str %ax /* Store task register value into AX */ + mov $0x28, %ax /* Store TSS GDT selector into AX */ + or $3, %ax + ltr %ax /* Load the task register */ + retq diff --git a/sys/arch/amd64/tss.c b/sys/arch/amd64/tss.c new file mode 100644 index 0000000..3463291 --- /dev/null +++ b/sys/arch/amd64/tss.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2023 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +__MODULE_NAME("TSS"); +__KERNEL_META("$Hyra$: tss.c, Ian Marco Moffett, " + "AMD64 Task state segment code"); + +static void +alloc_resources(struct cpu_info *cpu) +{ + struct tss_entry *tss; + + /* + * Allocate TSS entries for this CPU + */ + if (cpu->tss == NULL) { + /* Allocate a TSS for this CPU */ + tss = dynalloc(sizeof(*tss)); + if (tss == NULL) + panic("Failed to alloc %d bytes for TSS\n", sizeof(*tss)); + memset(tss, 0, sizeof(*tss)); + cpu->tss = tss; + } +} + +void +write_tss(struct cpu_info *cpu, struct tss_desc *desc) +{ + uintptr_t tss_base; + + alloc_resources(cpu); + + tss_base = (uintptr_t)cpu->tss; + + /* + * XXX: The AVL (Available for use by system software) + * bit is ignored by hardware and it is up to us + * to decide how to use it... As of now, it is useless + * to us and shall remain 0. + */ + desc->p = 1; /* Must be present to be valid! */ + desc->g = 0; /* Granularity -> 0 */ + desc->avl = 0; /* Not used */ + desc->dpl = 0; /* Descriptor Privilege Level -> 0 */ + desc->type = 0x9; /* For TSS -> 0x9 (0b1001) */ + + desc->base_lo16 = __SHIFTOUT(tss_base, __MASK(16)); + desc->base_mid24 = __SHIFTOUT(tss_base, __MASK(8) << 24); + desc->base_mid32 = __SHIFTOUT(tss_base, __MASK(32) << 32); +} diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h index e93e8a2..9645aac 100644 --- a/sys/include/arch/amd64/cpu.h +++ b/sys/include/arch/amd64/cpu.h @@ -32,6 +32,7 @@ #include #include +#include #define this_cpu() amd64_this_cpu() #define get_bsp() amd64_get_bsp() @@ -53,6 +54,7 @@ struct cpu_info { /* AMD64 */ volatile size_t lapic_tmr_freq; + volatile struct tss_entry *tss; }; struct cpu_info *amd64_this_cpu(void); diff --git a/sys/include/arch/amd64/gdt.h b/sys/include/arch/amd64/gdt.h index e5a7492..2521627 100644 --- a/sys/include/arch/amd64/gdt.h +++ b/sys/include/arch/amd64/gdt.h @@ -73,6 +73,7 @@ gdt_load(struct gdtr *gdtr) } extern struct gdt_entry g_gdt[256]; +extern struct gdt_entry *g_gdt_tss; extern struct gdtr g_gdtr; #endif /* !AMD64_GDT_H_ */ diff --git a/sys/include/arch/amd64/tss.h b/sys/include/arch/amd64/tss.h new file mode 100644 index 0000000..502cf9e --- /dev/null +++ b/sys/include/arch/amd64/tss.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AMD64_TSS_H_ +#define _AMD64_TSS_H_ + +#include +#include + +/* + * cpu_info is from machine/cpu.h + * + * XXX: machine/cpu.h includes this header + * so we must create this as including + * machine/cpu.h will not do anything... + */ +struct cpu_info; + +/* + * A TSS entry (64-bit) + * + * See Intel SDM Section 8.2.1 - Task-State Segment (TSS) + */ +struct __packed tss_entry { + uint32_t reserved1; + uint32_t rsp0_lo; + uint32_t rsp0_hi; + uint32_t rsp1_lo; + uint32_t rsp1_hi; + uint32_t rsp2_lo; + uint32_t rsp2_hi; + uint64_t reserved2; + uint32_t ist1_lo; + uint32_t ist1_hi; + uint32_t ist2_lo; + uint32_t ist2_hi; + uint32_t ist3_lo; + uint32_t ist3_hi; + uint32_t ist4_lo; + uint32_t ist4_hi; + uint32_t ist5_lo; + uint32_t ist5_hi; + uint32_t ist6_lo; + uint32_t ist6_hi; + uint32_t ist7_lo; + uint32_t ist7_hi; + uint64_t reserved3; + uint16_t reserved4; + uint16_t io_base; +}; + +/* + * TSS descriptor (64-bit) + * + * The TSS descriptor describes the location + * of the TSS segments among other things... + * + * See Intel SDM Section 8.2.3 - TSS Descriptor in 64-bit mode + */ +struct __packed tss_desc { + uint16_t seglimit; + uint16_t base_lo16; + uint8_t base_mid24; + uint8_t type : 4; + uint8_t zero : 1; + uint8_t dpl : 2; + uint8_t p : 1; + uint8_t seglimit_hi : 4; + uint8_t avl : 1; + uint8_t unused : 2; + uint8_t g : 1; + uint8_t base_mid32; + uint32_t base_hi32; + uint32_t reserved; +}; + +void write_tss(struct cpu_info *cpu, struct tss_desc *desc); +void tss_load(void); /* In tss.S */ + +#endif /* _!_AMD64_TSS_H_ */ -- cgit v1.2.3