From 8775a43cf5267abba09195caf0031960d6cb2434 Mon Sep 17 00:00:00 2001 From: sigsegv7 Date: Wed, 18 Oct 2023 18:00:49 -0400 Subject: kernel/amd64: lapic: Add basic x2APIC support Signed-off-by: sigsegv7 --- sys/include/arch/amd64/lapicvar.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'sys/include/arch') diff --git a/sys/include/arch/amd64/lapicvar.h b/sys/include/arch/amd64/lapicvar.h index 98b66ef..67cb277 100644 --- a/sys/include/arch/amd64/lapicvar.h +++ b/sys/include/arch/amd64/lapicvar.h @@ -54,6 +54,13 @@ #define IA32_APIC_BASE_MSR 0x1B +/* + * The x2APIC register space is accessed via + * RDMSR/WRMSR instructions. The below defines + * the base MSR address for the register space. + */ +#define x2APIC_MSR_BASE 0x00000800 + /* * To hardware enable, OR the value * of the IA32_APIC_BASE MSR with @@ -70,6 +77,7 @@ */ #define LAPIC_HW_ENABLE __BIT(11) #define LAPIC_SW_ENABLE (__BIT(8) | 0xFF) +#define x2APIC_ENABLE_SHIFT 10 /* The initial logical APIC ID to be set */ #define LAPIC_STARTUP_LID 0x1 -- cgit v1.2.3