From 70f860f211a59abdca8b0a11417b9781403fd647 Mon Sep 17 00:00:00 2001
From: sigsegv7 <ian@vegaa.systems>
Date: Fri, 15 Sep 2023 01:44:51 -0400
Subject: kernel: Refactor headers

Signed-off-by: sigsegv7 <ian@vegaa.systems>
---
 sys/include/arch/amd64/cpuid.h     | 2 +-
 sys/include/arch/amd64/ioapic.h    | 2 +-
 sys/include/arch/amd64/ioapicvar.h | 6 +++---
 sys/include/arch/amd64/lapicvar.h  | 4 +++-
 sys/include/arch/amd64/msr.h       | 2 +-
 5 files changed, 9 insertions(+), 7 deletions(-)

(limited to 'sys/include/arch')

diff --git a/sys/include/arch/amd64/cpuid.h b/sys/include/arch/amd64/cpuid.h
index 9420477..2aeb47e 100644
--- a/sys/include/arch/amd64/cpuid.h
+++ b/sys/include/arch/amd64/cpuid.h
@@ -37,4 +37,4 @@
             : "=a" (a), "=b" (b), "=c" (c), "=d" (d)    \
             : "0" (level))
 
-#endif  /* _AMD64_CPUID_H_ */
+#endif  /* !_AMD64_CPUID_H_ */
diff --git a/sys/include/arch/amd64/ioapic.h b/sys/include/arch/amd64/ioapic.h
index 1caee27..81c8198 100644
--- a/sys/include/arch/amd64/ioapic.h
+++ b/sys/include/arch/amd64/ioapic.h
@@ -39,4 +39,4 @@ void ioapic_gsi_unmask(uint8_t irq);
 void ioapic_set_base(void *mmio_base);
 void ioapic_init(void);
 
-#endif  /* _AMD64_IOAPIC_H_ */
+#endif  /* !_AMD64_IOAPIC_H_ */
diff --git a/sys/include/arch/amd64/ioapicvar.h b/sys/include/arch/amd64/ioapicvar.h
index 1e39fb6..40691cc 100644
--- a/sys/include/arch/amd64/ioapicvar.h
+++ b/sys/include/arch/amd64/ioapicvar.h
@@ -27,8 +27,8 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef _IOAPICVAR_H_
-#define _IOAPICVAR_H_
+#ifndef _AMD64_IOAPICVAR_H_
+#define _AMD64_IOAPICVAR_H_
 
 #include <sys/types.h>
 
@@ -54,4 +54,4 @@ union ioapic_redentry {
     uint64_t value;
 };
 
-#endif  /* _IOAPICVAR_H_ */
+#endif  /* !_AMD64_IOAPICVAR_H_ */
diff --git a/sys/include/arch/amd64/lapicvar.h b/sys/include/arch/amd64/lapicvar.h
index c6f9c0c..262dec0 100644
--- a/sys/include/arch/amd64/lapicvar.h
+++ b/sys/include/arch/amd64/lapicvar.h
@@ -47,4 +47,6 @@
 #define LAPIC_ERR           0x0280U     /* Error Status Register */
 #define LAPIC_DCR           0x03E0U     /* Divide Configuration Register (for timer) */
 
-#endif  /* _AMD64_LAPICVAR_H_ */
+#define IA32_APIC_BASE_MSR 0x1B
+
+#endif  /* !_AMD64_LAPICVAR_H_ */
diff --git a/sys/include/arch/amd64/msr.h b/sys/include/arch/amd64/msr.h
index e466fe9..9d3a8bf 100644
--- a/sys/include/arch/amd64/msr.h
+++ b/sys/include/arch/amd64/msr.h
@@ -60,4 +60,4 @@ wrmsr(uint32_t msr_addr, uint64_t value)
     );
 }
 
-#endif  /* _AMD64_MSR_H_ */
+#endif  /* !_AMD64_MSR_H_ */
-- 
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