From f53ac3212fe8f07c99aef348e754aa8ab00081dc Mon Sep 17 00:00:00 2001 From: sigsegv7 Date: Sun, 12 Nov 2023 00:16:24 -0500 Subject: kernel/amd64: lapic: Remove ESR support ESR support should be added later on; there is no need for it as of now... Signed-off-by: sigsegv7 --- sys/include/arch/amd64/lapicvar.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'sys/include/arch/amd64/lapicvar.h') diff --git a/sys/include/arch/amd64/lapicvar.h b/sys/include/arch/amd64/lapicvar.h index 2ad1a09..6edbeb5 100644 --- a/sys/include/arch/amd64/lapicvar.h +++ b/sys/include/arch/amd64/lapicvar.h @@ -91,10 +91,17 @@ /* LVT bits */ #define LAPIC_LVT_MASK __BIT(16) -/* Possible error bits within ESR */ -#define ESR_REDIR_IPI __BIT(4) /* Redirectible IPI */ -#define ESR_SIV __BIT(5) /* Send Illegal Vector */ -#define ESR_RIV __BIT(6) /* Received Illegal Vector */ -#define ESR_IRA __BIT(7) /* Illegal Register Address */ +/* + * Local APIC Interrupt stack [IST VALUE]. + * + * This value should be non-zero and reserved + * for only 1 interrupt vector to prevent clobbering + * of the interrupt stacks. + * + * XXX TODO: The value is correctly 0, however, this needs + * to be updated to a non-zero value as soon as + * possible. + */ +#define LAPIC_TMR_INTSTACK 0 #endif /* !_AMD64_LAPICVAR_H_ */ -- cgit v1.2.3