From 98ccb3a2d41015b42d46d8b382decc755a003c3f Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Tue, 4 Jun 2024 13:41:11 -0400 Subject: project: Initial commit Signed-off-by: Ian Moffett --- sys/include/arch/amd64/cpu.h | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 sys/include/arch/amd64/cpu.h (limited to 'sys/include/arch/amd64/cpu.h') diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h new file mode 100644 index 0000000..efa60ad --- /dev/null +++ b/sys/include/arch/amd64/cpu.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_CPU_H_ +#define _MACHINE_CPU_H_ + +#include +#include + +struct cpu_info { + uint32_t apicid; +}; + +void cpu_startup(void); + + +#endif /* !_MACHINE_CPU_H_ */ -- cgit v1.2.3 From dbfcd0e88e471564392549652d0bde2a967c34f4 Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Wed, 5 Jun 2024 20:58:51 -0400 Subject: kernel/amd64: Add initial LAPIC code Signed-off-by: Ian Moffett --- sys/arch/amd64/amd64/acpi_machdep.c | 2 + sys/arch/amd64/amd64/lapic.c | 214 ++++++++++++++++++++++++++++++++++++ sys/arch/amd64/amd64/machdep.c | 13 +++ sys/include/arch/amd64/cpu.h | 3 +- sys/include/arch/amd64/lapic.h | 39 +++++++ sys/include/arch/amd64/lapicvar.h | 85 ++++++++++++++ sys/include/arch/amd64/msr.h | 1 + 7 files changed, 356 insertions(+), 1 deletion(-) create mode 100644 sys/arch/amd64/amd64/lapic.c create mode 100644 sys/include/arch/amd64/lapic.h create mode 100644 sys/include/arch/amd64/lapicvar.h (limited to 'sys/include/arch/amd64/cpu.h') diff --git a/sys/arch/amd64/amd64/acpi_machdep.c b/sys/arch/amd64/amd64/acpi_machdep.c index d1686df..3bcdc9d 100644 --- a/sys/arch/amd64/amd64/acpi_machdep.c +++ b/sys/arch/amd64/amd64/acpi_machdep.c @@ -33,6 +33,7 @@ #include #include #include +#include #define pr_trace(fmt, ...) kprintf("acpi: " fmt, ##__VA_ARGS__) @@ -50,6 +51,7 @@ acpi_init_madt(void) cur = (uint8_t *)(madt + 1); end = (uint8_t *)madt + madt->hdr.length; + g_lapic_base = madt->lapic_addr; while (cur < end) { apichdr = (void *)cur; diff --git a/sys/arch/amd64/amd64/lapic.c b/sys/arch/amd64/amd64/lapic.c new file mode 100644 index 0000000..f61715d --- /dev/null +++ b/sys/arch/amd64/amd64/lapic.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define pr_trace(fmt, ...) kprintf("lapic: " fmt, ##__VA_ARGS__) + +/* + * Only calls pr_trace if we are the BSP. + */ +#define bsp_trace(...) do { \ + uint64_t msr_val; \ + \ + msr_val = rdmsr(IA32_APIC_BASE_MSR); \ + if (ISSET(msr_val, BIT(8))) { \ + pr_trace(__VA_ARGS__); \ + } \ + } while (0); + +uintptr_t g_lapic_base = 0; + +/* + * Returns true if LAPIC is supported. + * + * LAPIC is supported if CPUID.(EAX=1H):EDX[9] == 1 + */ +static inline bool +lapic_supported(void) +{ + uint32_t eax, edx, tmp; + + CPUID(0x00000001, eax, tmp, tmp, edx); + return ISSET(edx, BIT(9)); +} + +/* + * Checks if the processor supports x2APIC + * mode. Returns true if so. + */ +static inline bool +lapic_has_x2apic(void) +{ + uint32_t ecx, tmp; + + CPUID(0x00000001, tmp, tmp, ecx, tmp); + return ISSET(ecx, BIT(21)); +} + +/* + * Reads a 32 bit value from Local APIC + * register space. + * + * @reg: Register to read from. + */ +static inline uint64_t +lapic_readl(uint32_t reg) +{ + void *addr; + const struct cpu_info *ci = this_cpu(); + + if (!ci->has_x2apic) { + addr = (void *)(g_lapic_base + reg); + return mmio_read32(addr); + } else { + reg >>= 4; + return rdmsr(x2APIC_MSR_BASE + reg); + } +} + +/* + * Writes a 32 bit value to Local APIC + * register space. + * + * @reg: Register to write to. + */ +static inline void +lapic_writel(uint32_t reg, uint64_t val) +{ + void *addr; + const struct cpu_info *ci = this_cpu(); + + if (!ci->has_x2apic) { + addr = (void *)(g_lapic_base + reg); + mmio_write32(addr, val); + } else { + reg >>= 4; + wrmsr(x2APIC_MSR_BASE + reg, val); + } +} + +/* + * Set bits within a LAPIC register + * without overwriting the whole thing. + * + * @reg: Reg with bits to be set. + * @value: Value in reg will be ORd with this. + */ +static inline void +lapic_reg_set(uint32_t reg, uint32_t value) +{ + uint32_t old; + + old = lapic_readl(reg); + lapic_writel(reg, old | value); +} + +/* + * Clear bits within a LAPIC register + * without overwriting the whole thing. + * + * @reg: Reg with bits to be cleared. + * @value: Value in reg will be cleared by this value. + */ +static inline void +lapic_reg_clear(uint32_t reg, uint32_t value) +{ + uint32_t old; + + old = lapic_readl(reg); + lapic_writel(reg, old & ~(value)); +} + +/* + * Hardware and software enable the Local APIC + * through IA32_APIC_BASE_MSR + */ +static inline void +lapic_enable(const struct cpu_info *ci) +{ + uint64_t tmp; + + /* Hardware enable the Local APIC */ + tmp = rdmsr(IA32_APIC_BASE_MSR); + tmp |= ci->has_x2apic << x2APIC_ENABLE_SHIFT; + wrmsr(IA32_APIC_BASE_MSR, tmp | LAPIC_HW_ENABLE); + + /* Software enable the Local APIC */ + lapic_reg_set(LAPIC_SVR, LAPIC_SW_ENABLE); +} + +/* + * Reads the Local APIC ID of the current + * processor. + */ +static inline uint32_t +lapic_read_id(const struct cpu_info *ci) +{ + if (!ci->has_x2apic) { + return (lapic_readl(LAPIC_ID) >> 24) & 0xF; + } else { + return lapic_readl(LAPIC_ID); + } +} + +void +lapic_init(void) +{ + struct cpu_info *ci = this_cpu(); + + /* + * Hyra currently depends on the existance + * of a Local APIC. + */ + if (!lapic_supported()) { + panic("This machine does not support LAPIC!\n"); + } + + /* Ensure the LAPIC base is valid */ + if (g_lapic_base == 0) { + panic("Invalid LAPIC base\n"); + } + + ci->has_x2apic = lapic_has_x2apic(); + lapic_enable(ci); + + ci->apicid = lapic_read_id(ci); + bsp_trace("BSP LAPIC enabled in %s mode (id=%d)\n", + ci->has_x2apic ? "x2APIC" : "xAPIC", ci->apicid); +} diff --git a/sys/arch/amd64/amd64/machdep.c b/sys/arch/amd64/amd64/machdep.c index 275c23e..983a480 100644 --- a/sys/arch/amd64/amd64/machdep.c +++ b/sys/arch/amd64/amd64/machdep.c @@ -34,6 +34,7 @@ #include #include #include +#include #if defined(__SPECTRE_IBRS) #define SPECTRE_IBRS __SPECTRE_IBRS @@ -76,6 +77,16 @@ try_mitigate_spectre(void) ibrs_enable(); } +/* + * Get the descriptor for the currently + * running processor. + */ +struct cpu_info * +this_cpu(void) +{ + return (void *)amd64_read_gs_base(); +} + void cpu_startup(void) { @@ -84,5 +95,7 @@ cpu_startup(void) setup_vectors(); amd64_write_gs_base((uintptr_t)&g_bsp_ci); + try_mitigate_spectre(); + lapic_init(); } diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h index efa60ad..4e5baf1 100644 --- a/sys/include/arch/amd64/cpu.h +++ b/sys/include/arch/amd64/cpu.h @@ -35,9 +35,10 @@ struct cpu_info { uint32_t apicid; + uint8_t has_x2apic : 1; }; void cpu_startup(void); - +struct cpu_info *this_cpu(void); #endif /* !_MACHINE_CPU_H_ */ diff --git a/sys/include/arch/amd64/lapic.h b/sys/include/arch/amd64/lapic.h new file mode 100644 index 0000000..8a6bb14 --- /dev/null +++ b/sys/include/arch/amd64/lapic.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_LAPIC_H_ +#define _MACHINE_LAPIC_H_ + +#include + +void lapic_init(void); + +extern uintptr_t g_lapic_base; + +#endif /* !_MACHINE_LAPIC_H_ */ diff --git a/sys/include/arch/amd64/lapicvar.h b/sys/include/arch/amd64/lapicvar.h new file mode 100644 index 0000000..e224e43 --- /dev/null +++ b/sys/include/arch/amd64/lapicvar.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_LAPICVAR_H_ +#define _MACHINE_LAPICVAR_H_ + +#include + +/* LAPIC register offsets */ +#define LAPIC_ID 0x0020U /* ID Register */ +#define LAPIC_VERSION 0x0030U /* Version Register */ +#define LAPIC_TPR 0x0080U /* Task Priority Register */ +#define LAPIC_APR 0x0090U /* Arbitration Priority Register */ +#define LAPIC_PPR 0x00A0U /* Processor Priority Register */ +#define LAPIC_EOI 0x00B0U /* End Of Interrupt Register */ +#define LAPIC_RRD 0x00C0U /* Remote Read Register */ +#define LAPIC_LDR 0x00D0U /* Logical Destination Register */ +#define LAPIC_DFR 0x00E0U /* Destination Format Register */ +#define LAPIC_SVR 0x00F0U /* Spurious Vector Register */ +#define LAPIC_ISR 0x0100U /* In service register (max=0x0220) */ +#define LAPIC_TMR 0x0180U /* Trigger Mode Register (max=0x0220) */ +#define LAPIC_IRR 0x0200U /* Interrupt Request Register (max=0x0270) */ +#define LAPIC_ERR 0x0280U /* Error Status Register */ +#define LAPIC_ICRLO 0x0300U /* Interrupt Command Low Register */ +#define LAPIC_ICRHI 0x0310U /* Interrupt Command High Register */ +#define LAPIC_LVT_TMR 0x0320U /* LVT Timer Register */ +#define LAPIC_DCR 0x03E0U /* Divide Configuration Register (for timer) */ +#define LAPIC_INIT_CNT 0x0380U /* Initial Count Register (for timer) */ +#define LAPIC_CUR_CNT 0x0390U /* Current Count Register (for timer) */ + +/* + * The x2APIC register space is accessed via + * RDMSR/WRMSR instructions. The below defines + * the base MSR address for the register space. + */ +#define x2APIC_MSR_BASE 0x00000800 + +/* + * To hardware enable, OR the value of the IA32_APIC_BASE + * MSR with LAPIC_HW_ENABLE and rewrite it. + * + * To software enable, OR the value of the SVR with + * LAPIC_SW_ENABLE and rewrite it. + * + * LAPIC_SW_ENABLE has the low 8 bits set as some hardware + * requires the spurious vector to be hardwired to 1s so + * we'll go with that to be safe. + */ +#define LAPIC_HW_ENABLE BIT(11) +#define LAPIC_SW_ENABLE (BIT(8) | 0xFF) +#define x2APIC_ENABLE_SHIFT 10 + +/* LVT bits */ +#define LAPIC_LVT_MASK BIT(16) +#define LVT_TMR_ONESHOT 0x00 +#define LVT_TMR_PERIODIC 0x01 +#define LVT_TMR_TSC_DEADLINE 0x02 + +#endif /* !_MACHINE_LAPICVAR_H_ */ diff --git a/sys/include/arch/amd64/msr.h b/sys/include/arch/amd64/msr.h index 6ad95f1..d3d0c9a 100644 --- a/sys/include/arch/amd64/msr.h +++ b/sys/include/arch/amd64/msr.h @@ -32,6 +32,7 @@ #define IA32_SPEC_CTL 0x00000048 #define IA32_KERNEL_GS_BASE 0xC0000102 +#define IA32_APIC_BASE_MSR 0x0000001B #if !defined(__ASSEMBLER__) static inline uint64_t -- cgit v1.2.3 From 79afbbb41dee4bb24d2cad8234beacbd7a7e7a9b Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Thu, 6 Jun 2024 15:50:23 -0400 Subject: kernel/amd64: lapic: Add support for LAPIC timer Signed-off-by: Ian Moffett --- sys/arch/amd64/amd64/lapic.c | 109 ++++++++++++++++++++++++++++++++++++++ sys/arch/amd64/amd64/lapic_intr.S | 9 ++++ sys/include/arch/amd64/cpu.h | 1 + 3 files changed, 119 insertions(+) create mode 100644 sys/arch/amd64/amd64/lapic_intr.S (limited to 'sys/include/arch/amd64/cpu.h') diff --git a/sys/arch/amd64/amd64/lapic.c b/sys/arch/amd64/amd64/lapic.c index f61715d..823e830 100644 --- a/sys/arch/amd64/amd64/lapic.c +++ b/sys/arch/amd64/amd64/lapic.c @@ -32,11 +32,15 @@ #include #include #include +#include +#include +#include #include #include #include #include #include +#include #define pr_trace(fmt, ...) kprintf("lapic: " fmt, ##__VA_ARGS__) @@ -52,8 +56,12 @@ } \ } while (0); +static struct timer lapic_timer; +static uint8_t lapic_timer_vec = 0; uintptr_t g_lapic_base = 0; +void lapic_tmr_isr(void); + /* * Returns true if LAPIC is supported. * @@ -123,6 +131,62 @@ lapic_writel(uint32_t reg, uint64_t val) } } +/* + * Starts the Local APIC countdown timer... + * + * @mask: True to mask timer. + * @mode: Timer mode. + * @count: Count to start at. + */ +static inline void +lapic_timer_start(bool mask, uint8_t mode, uint32_t count) +{ + uint32_t tmp; + + tmp = (mode << 17) | (mask << 16) | lapic_timer_vec; + lapic_writel(LAPIC_LVT_TMR, tmp); + lapic_writel(LAPIC_DCR, 0); + lapic_writel(LAPIC_INIT_CNT, count); +} + +/* + * Start Local APIC timer oneshot with number + * of ticks to count down from. + * + * @mask: If `true', timer will be masked, `count' should be 0. + * @count: Number of ticks. + */ +static void +lapic_timer_oneshot(bool mask, uint32_t count) +{ + lapic_timer_start(mask, LVT_TMR_ONESHOT, count); +} + +/* + * Start Local APIC timer oneshot in microseconds. + * + * @us: Microseconds. + */ +static void +lapic_timer_oneshot_us(size_t usec) +{ + uint64_t ticks; + struct cpu_info *ci = this_cpu(); + + ticks = usec * (ci->lapic_tmr_freq / 1000000); + lapic_timer_oneshot(false, ticks); +} + +/* + * Stops the Local APIC timer + */ +static void +lapic_timer_stop(void) +{ + lapic_writel(LAPIC_LVT_TMR, LAPIC_LVT_MASK); + lapic_writel(LAPIC_INIT_CNT, 0); +} + /* * Set bits within a LAPIC register * without overwriting the whole thing. @@ -187,10 +251,37 @@ lapic_read_id(const struct cpu_info *ci) } } +/* + * Init the Local APIC timer and return + * the frequency. + */ +static size_t +lapic_timer_init(void) +{ + uint16_t ticks_start, ticks_end; + size_t ticks_total, freq; + const uint16_t MAX_SAMPLES = 0xFFFF; + + lapic_timer_stop(); + i8254_set_reload(MAX_SAMPLES); + ticks_start = i8254_get_count(); + + lapic_writel(LAPIC_INIT_CNT, MAX_SAMPLES); + while (lapic_readl(LAPIC_CUR_CNT) != 0); + + ticks_end = i8254_get_count(); + ticks_total = ticks_start - ticks_end; + + freq = (MAX_SAMPLES / ticks_total) * I8254_DIVIDEND; + lapic_timer_stop(); + return freq; +} + void lapic_init(void) { struct cpu_info *ci = this_cpu(); + tmrr_status_t tmr_status; /* * Hyra currently depends on the existance @@ -200,6 +291,12 @@ lapic_init(void) panic("This machine does not support LAPIC!\n"); } + /* Allocate a vector if needed */ + if (lapic_timer_vec == 0) { + lapic_timer_vec = intr_alloc_vector(); + idt_set_desc(lapic_timer_vec, IDT_INT_GATE, ISR(lapic_tmr_isr), 0); + } + /* Ensure the LAPIC base is valid */ if (g_lapic_base == 0) { panic("Invalid LAPIC base\n"); @@ -209,6 +306,18 @@ lapic_init(void) lapic_enable(ci); ci->apicid = lapic_read_id(ci); + ci->lapic_tmr_freq = lapic_timer_init(); bsp_trace("BSP LAPIC enabled in %s mode (id=%d)\n", ci->has_x2apic ? "x2APIC" : "xAPIC", ci->apicid); + + /* Try to register the timer */ + lapic_timer.name = "LAPIC_INTEGRATED_TIMER"; + lapic_timer.stop = lapic_timer_stop; + lapic_timer.oneshot_us = lapic_timer_oneshot_us; + tmr_status = register_timer(TIMER_SCHED, &lapic_timer); + + /* This should not happen but handle it just in case */ + if (__unlikely(tmr_status != TMRR_SUCCESS)) { + panic("Failed to register %s\n", lapic_timer.name); + } } diff --git a/sys/arch/amd64/amd64/lapic_intr.S b/sys/arch/amd64/amd64/lapic_intr.S new file mode 100644 index 0000000..295de2d --- /dev/null +++ b/sys/arch/amd64/amd64/lapic_intr.S @@ -0,0 +1,9 @@ +#include + + .text + .globl lapic_tmr_isr +lapic_tmr_isr: + push_trapframe $0 + mov %rsp, %rdi + pop_trapframe + iretq diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h index 4e5baf1..92d2356 100644 --- a/sys/include/arch/amd64/cpu.h +++ b/sys/include/arch/amd64/cpu.h @@ -36,6 +36,7 @@ struct cpu_info { uint32_t apicid; uint8_t has_x2apic : 1; + size_t lapic_tmr_freq; }; void cpu_startup(void); -- cgit v1.2.3 From a84cacff59d6e31c05b6f9eddebf28dbb418b303 Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Thu, 6 Jun 2024 17:46:39 -0400 Subject: kernel/amd64: tss: Add support for TSS Signed-off-by: Ian Moffett --- sys/arch/amd64/amd64/machdep.c | 12 +++ sys/arch/amd64/amd64/tss.c | 177 +++++++++++++++++++++++++++++++++++++++++ sys/include/arch/amd64/cpu.h | 2 + sys/include/arch/amd64/gdt.h | 1 + sys/include/arch/amd64/intr.h | 4 + sys/include/arch/amd64/tss.h | 121 ++++++++++++++++++++++++++++ 6 files changed, 317 insertions(+) create mode 100644 sys/arch/amd64/amd64/tss.c create mode 100644 sys/include/arch/amd64/tss.h (limited to 'sys/include/arch/amd64/cpu.h') diff --git a/sys/arch/amd64/amd64/machdep.c b/sys/arch/amd64/amd64/machdep.c index 983a480..2fe71a9 100644 --- a/sys/arch/amd64/amd64/machdep.c +++ b/sys/arch/amd64/amd64/machdep.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -67,6 +68,16 @@ setup_vectors(void) idt_set_desc(0xE, IDT_TRAP_GATE, ISR(page_fault), 0); } +static inline void +init_tss(struct cpu_info *ci) +{ + struct tss_desc *desc; + + desc = (struct tss_desc *)&g_gdt_data[GDT_TSS]; + write_tss(ci, desc); + tss_load(); +} + static void try_mitigate_spectre(void) { @@ -95,6 +106,7 @@ cpu_startup(void) setup_vectors(); amd64_write_gs_base((uintptr_t)&g_bsp_ci); + init_tss(&g_bsp_ci); try_mitigate_spectre(); lapic_init(); diff --git a/sys/arch/amd64/amd64/tss.c b/sys/arch/amd64/amd64/tss.c new file mode 100644 index 0000000..5aab74a --- /dev/null +++ b/sys/arch/amd64/amd64/tss.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Allocates memory for TSS and kernel + * stack. + * + * XXX: Kernel stack is allocated from + * vm_alloc_frame() + */ +static void +alloc_resources(struct cpu_info *ci) +{ + const size_t STACK_SIZE = 0x1000; + struct tss_entry *tss; + static uintptr_t rsp0_base, rsp0; + + if (ci->tss == NULL) { + tss = dynalloc(sizeof(*tss)); + + if (tss == NULL) { + panic("Failed to alloc TSS\n"); + } + + memset(tss, 0, sizeof(*tss)); + rsp0_base = vm_alloc_frame(1); + + if (rsp0_base == 0) { + panic("Could not allocate RSP0 base\n"); + } + + rsp0 = rsp0_base + STACK_SIZE; + tss->rsp0_lo = rsp0 & 0xFFFFFFFF; + tss->rsp0_hi = (rsp0 >> 32) & 0xFFFFFFFF; + ci->tss = tss; + } +} + +/* + * Update interrupt stack table entry `istno' with `stack' + * + * @stack: Interrupt stack. + * @istno: IST number, must be 1-based. + * + * Returns 0 on success. + */ +int +tss_update_ist(struct cpu_info *ci, union tss_stack stack, uint8_t istno) +{ + volatile struct tss_entry *tss = ci->tss; + + __assert(tss != NULL); + + switch (istno) { + case 1: + tss->ist1_lo = stack.top_lo; + tss->ist1_hi = stack.top_hi; + break; + case 2: + tss->ist2_lo = stack.top_lo; + tss->ist2_hi = stack.top_hi; + break; + case 3: + tss->ist3_lo = stack.top_lo; + tss->ist3_hi = stack.top_hi; + break; + case 4: + tss->ist4_lo = stack.top_lo; + tss->ist4_hi = stack.top_hi; + break; + case 5: + tss->ist5_lo = stack.top_lo; + tss->ist5_hi = stack.top_hi; + break; + case 6: + tss->ist6_lo = stack.top_lo; + tss->ist6_hi = stack.top_hi; + break; + case 7: + tss->ist7_lo = stack.top_lo; + tss->ist7_hi = stack.top_hi; + break; + default: + return -EINVAL; + }; + + return 0; +} + +/* + * Allocates TSS stack. + * + * @entry_out: Pointer to location where allocated entry + * will be sent. + * + * Returns 0 on success. + */ +int +tss_alloc_stack(union tss_stack *entry_out, size_t size) +{ + uintptr_t base = (uintptr_t)dynalloc(size); + + if (base == 0) { + return -ENOMEM; + } + + entry_out->top = base + size; + return 0; +} + +void +write_tss(struct cpu_info *ci, struct tss_desc *desc) +{ + volatile struct tss_entry *tss; + uintptr_t tss_base; + + alloc_resources(ci); + tss_base = (uintptr_t)ci->tss; + + /* + * XXX: The AVL (Available for use by system software) + * bit is ignored by hardware and it is up to us + * to decide how to use it... As of now, it is useless + * to us and shall remain 0. + */ + desc->seglimit = sizeof(struct tss_entry); + desc->p = 1; /* Must be present to be valid! */ + desc->g = 0; /* Granularity -> 0 */ + desc->avl = 0; /* Not used */ + desc->dpl = 0; /* Descriptor Privilege Level -> 0 */ + desc->type = 0x9; /* For TSS -> 0x9 (0b1001) */ + + desc->base_lo16 = tss_base & 0xFFFF; + desc->base_mid8 = (tss_base >> 16) & 0xFF; + desc->base_hi_mid8 = (tss_base >> 24) & 0xFF; + desc->base_hi32 = (tss_base >> 32) & 0xFFFFFFFF; + + tss = ci->tss; + tss->io_base = 0xFF; /* Disallow ring 3 port I/O */ +} diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h index 92d2356..ef2eb78 100644 --- a/sys/include/arch/amd64/cpu.h +++ b/sys/include/arch/amd64/cpu.h @@ -32,11 +32,13 @@ #include #include +#include struct cpu_info { uint32_t apicid; uint8_t has_x2apic : 1; size_t lapic_tmr_freq; + struct tss_entry *tss; }; void cpu_startup(void); diff --git a/sys/include/arch/amd64/gdt.h b/sys/include/arch/amd64/gdt.h index 6f8a914..ce7dd60 100644 --- a/sys/include/arch/amd64/gdt.h +++ b/sys/include/arch/amd64/gdt.h @@ -6,6 +6,7 @@ #define KERNEL_CS 0x08 #define KERNEL_DS 0x10 +#define GDT_TSS 5 struct __packed gdt_entry { uint16_t limit; diff --git a/sys/include/arch/amd64/intr.h b/sys/include/arch/amd64/intr.h index cceab6f..3f0da77 100644 --- a/sys/include/arch/amd64/intr.h +++ b/sys/include/arch/amd64/intr.h @@ -32,6 +32,10 @@ #include +#define IST_SCHED 1U +#define IST_HW_IRQ 2U +#define IST_SW_INT 3U + int intr_alloc_vector(void); #endif diff --git a/sys/include/arch/amd64/tss.h b/sys/include/arch/amd64/tss.h new file mode 100644 index 0000000..347192d --- /dev/null +++ b/sys/include/arch/amd64/tss.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_TSS_H_ +#define _MACHINE_TSS_H_ + +#include +#include + +struct cpu_info; + +/* + * A TSS entry (64-bit) + * + * See Intel SDM Section 8.2.1 - Task-State Segment (TSS) + */ +struct __packed tss_entry { + uint32_t reserved1; + uint32_t rsp0_lo; + uint32_t rsp0_hi; + uint32_t rsp1_lo; + uint32_t rsp1_hi; + uint32_t rsp2_lo; + uint32_t rsp2_hi; + uint64_t reserved2; + uint32_t ist1_lo; + uint32_t ist1_hi; + uint32_t ist2_lo; + uint32_t ist2_hi; + uint32_t ist3_lo; + uint32_t ist3_hi; + uint32_t ist4_lo; + uint32_t ist4_hi; + uint32_t ist5_lo; + uint32_t ist5_hi; + uint32_t ist6_lo; + uint32_t ist6_hi; + uint32_t ist7_lo; + uint32_t ist7_hi; + uint64_t reserved3; + uint16_t reserved4; + uint16_t io_base; +}; + +/* + * TSS descriptor (64-bit) + * + * The TSS descriptor describes the location + * of the TSS segments among other things... + * + * See Intel SDM Section 8.2.3 - TSS Descriptor in 64-bit mode + */ +struct __packed tss_desc { + uint16_t seglimit; + uint16_t base_lo16; + uint8_t base_mid8; + uint8_t type : 4; + uint8_t zero : 1; + uint8_t dpl : 2; + uint8_t p : 1; + uint8_t seglimit_hi : 4; + uint8_t avl : 1; + uint8_t unused : 2; + uint8_t g : 1; + uint8_t base_hi_mid8; + uint32_t base_hi32; + uint32_t reserved; +}; + +/* + * Holds the address of the address pointing + * to the top of an interrupt stack. + */ +union tss_stack { + struct { + uint32_t top_lo; + uint32_t top_hi; + }; + uint64_t top; +}; + +__always_inline static inline void +tss_load(void) +{ + __ASMV("str %ax\n" + "mov $0x2B, %ax\n" + "ltr %ax" + ); +} + +int tss_alloc_stack(union tss_stack *entry_out, size_t size); +int tss_update_ist(struct cpu_info *ci, union tss_stack stack, uint8_t istno); +void write_tss(struct cpu_info *ci, struct tss_desc *desc); + +#endif /* !_MACHINE_TSS_H_ */ -- cgit v1.2.3 From 44ef655a0afc3d2c8aa305f94b412f9d89bec846 Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Sat, 8 Jun 2024 18:15:13 -0400 Subject: kernel/amd64: Pass CPU info to cpu_startup() Signed-off-by: Ian Moffett --- sys/arch/amd64/amd64/machdep.c | 9 +++++---- sys/include/arch/amd64/cpu.h | 3 ++- sys/kern/init_main.c | 2 +- 3 files changed, 8 insertions(+), 6 deletions(-) (limited to 'sys/include/arch/amd64/cpu.h') diff --git a/sys/arch/amd64/amd64/machdep.c b/sys/arch/amd64/amd64/machdep.c index 2fe71a9..82fa97b 100644 --- a/sys/arch/amd64/amd64/machdep.c +++ b/sys/arch/amd64/amd64/machdep.c @@ -45,7 +45,7 @@ int ibrs_enable(void); -static struct cpu_info g_bsp_ci = {0}; +struct cpu_info g_bsp_ci = {0}; static struct gdtr bsp_gdtr = { .limit = sizeof(struct gdt_entry) * 256 - 1, .offset = (uintptr_t)&g_gdt_data[0] @@ -99,15 +99,16 @@ this_cpu(void) } void -cpu_startup(void) +cpu_startup(struct cpu_info *ci) { gdt_load(&bsp_gdtr); idt_load(); setup_vectors(); - amd64_write_gs_base((uintptr_t)&g_bsp_ci); - init_tss(&g_bsp_ci); + amd64_write_gs_base((uintptr_t)ci); + init_tss(ci); try_mitigate_spectre(); + __ASMV("sti"); /* Unmask interrupts */ lapic_init(); } diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h index ef2eb78..84391ba 100644 --- a/sys/include/arch/amd64/cpu.h +++ b/sys/include/arch/amd64/cpu.h @@ -41,7 +41,8 @@ struct cpu_info { struct tss_entry *tss; }; -void cpu_startup(void); +void cpu_startup(struct cpu_info *ci); struct cpu_info *this_cpu(void); +extern struct cpu_info g_bsp_ci; #endif /* !_MACHINE_CPU_H_ */ diff --git a/sys/kern/init_main.c b/sys/kern/init_main.c index 6f17227..94fa8c0 100644 --- a/sys/kern/init_main.c +++ b/sys/kern/init_main.c @@ -49,7 +49,7 @@ main(void) vm_init(); /* Startup the BSP */ - cpu_startup(); + cpu_startup(&g_bsp_ci); /* Nothing left to do... halt */ cpu_reboot(REBOOT_HALT); -- cgit v1.2.3 From 55845113211400c9b1657ec3ce72b06a05efac4e Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Sat, 8 Jun 2024 18:19:51 -0400 Subject: kernel/amd64: Prepare for scheduler Signed-off-by: Ian Moffett --- sys/arch/amd64/amd64/lapic_intr.S | 2 + sys/arch/amd64/amd64/mp.c | 93 ++++++++++++++++++++++++++++++++++ sys/arch/amd64/conf/GENERIC | 3 ++ sys/include/arch/amd64/cpu.h | 4 ++ sys/include/sys/proc.h | 48 ++++++++++++++++++ sys/include/sys/sched.h | 39 +++++++++++++++ sys/include/sys/schedvar.h | 63 +++++++++++++++++++++++ sys/kern/init_main.c | 5 ++ sys/kern/kern_sched.c | 102 ++++++++++++++++++++++++++++++++++++++ 9 files changed, 359 insertions(+) create mode 100644 sys/arch/amd64/amd64/mp.c create mode 100644 sys/include/sys/proc.h create mode 100644 sys/include/sys/sched.h create mode 100644 sys/include/sys/schedvar.h create mode 100644 sys/kern/kern_sched.c (limited to 'sys/include/arch/amd64/cpu.h') diff --git a/sys/arch/amd64/amd64/lapic_intr.S b/sys/arch/amd64/amd64/lapic_intr.S index 295de2d..a3fa7e4 100644 --- a/sys/arch/amd64/amd64/lapic_intr.S +++ b/sys/arch/amd64/amd64/lapic_intr.S @@ -5,5 +5,7 @@ lapic_tmr_isr: push_trapframe $0 mov %rsp, %rdi + call sched_switch + call lapic_eoi pop_trapframe iretq diff --git a/sys/arch/amd64/amd64/mp.c b/sys/arch/amd64/amd64/mp.c new file mode 100644 index 0000000..9512aa6 --- /dev/null +++ b/sys/arch/amd64/amd64/mp.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define pr_trace(fmt, ...) kprintf("cpu_mp: " fmt, ##__VA_ARGS__) + +static volatile struct limine_smp_request g_smp_req = { + .id = LIMINE_SMP_REQUEST, + .revision = 0 +}; + +static void +ap_trampoline(struct limine_smp_info *si) +{ + struct spinlock lock = {0}; + struct cpu_info *ci; + + spinlock_acquire(&lock); + ci = dynalloc(sizeof(*ci)); + __assert(ci != NULL); + + memset(ci, 0, sizeof(*ci)); + cpu_startup(ci); + + spinlock_release(&lock); + sched_enter(); + + while (1); +} + +void +mp_bootstrap_aps(struct cpu_info *ci) +{ + struct limine_smp_response *resp = g_smp_req.response; + struct limine_smp_info **cpus; + size_t cpu_init_counter; + + /* Should not happen */ + __assert(resp != NULL); + + cpus = resp->cpus; + cpu_init_counter = resp->cpu_count - 1; + + if (resp->cpu_count == 1) { + pr_trace("CPU has 1 core, no APs to bootstrap...\n"); + return; + } + + pr_trace("Bootstrapping %d cores...\n", cpu_init_counter); + for (size_t i = 0; i < resp->cpu_count; ++i) { + if (ci->apicid == cpus[i]->lapic_id) { + pr_trace("Skip %d (BSP)... continue\n", ci->apicid); + continue; + } + + cpus[i]->goto_address = ap_trampoline; + } +} diff --git a/sys/arch/amd64/conf/GENERIC b/sys/arch/amd64/conf/GENERIC index ea6ba76..a7bbc81 100644 --- a/sys/arch/amd64/conf/GENERIC +++ b/sys/arch/amd64/conf/GENERIC @@ -1,2 +1,5 @@ // Kernel options option SPECTRE_IBRS no + +// Kernel constants +setval SCHED_NQUEUE 4 diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h index 84391ba..b5420a6 100644 --- a/sys/include/arch/amd64/cpu.h +++ b/sys/include/arch/amd64/cpu.h @@ -32,6 +32,7 @@ #include #include +#include #include struct cpu_info { @@ -39,10 +40,13 @@ struct cpu_info { uint8_t has_x2apic : 1; size_t lapic_tmr_freq; struct tss_entry *tss; + struct proc *curtd; }; void cpu_startup(struct cpu_info *ci); struct cpu_info *this_cpu(void); +void mp_bootstrap_aps(struct cpu_info *ci); + extern struct cpu_info g_bsp_ci; #endif /* !_MACHINE_CPU_H_ */ diff --git a/sys/include/sys/proc.h b/sys/include/sys/proc.h new file mode 100644 index 0000000..ba47a5c --- /dev/null +++ b/sys/include/sys/proc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_PROC_H_ +#define _SYS_PROC_H_ + +#include +#include +#if defined(_KERNEL) +#include +#include +#endif /* _KERNEL */ + +#if defined(_KERNEL) + +struct proc { + pid_t pid; + struct cpu_info *cpu; +}; + +#endif /* _KERNEL */ +#endif /* !_SYS_PROC_H_ */ diff --git a/sys/include/sys/sched.h b/sys/include/sys/sched.h new file mode 100644 index 0000000..33d546d --- /dev/null +++ b/sys/include/sys/sched.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_SCHED_H_ +#define _SYS_SCHED_H_ + +#if defined(_KERNEL) + +void sched_init(void); +void sched_enter(void); + +#endif /* _KERNEL */ +#endif /* !_SYS_SCHED_H_ */ diff --git a/sys/include/sys/schedvar.h b/sys/include/sys/schedvar.h new file mode 100644 index 0000000..00caeb4 --- /dev/null +++ b/sys/include/sys/schedvar.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_SCHEDVAR_H_ +#define _SYS_SCHEDVAR_H_ + +#include +#include +#include + +#if defined(_KERNEL) +#define DEFAULT_TIMESLICE_USEC 1050 +#define SHORT_TIMESLICE_USEC 10 + +#define SCHED_POLICY_MLFQ 0x00U /* Multilevel feedback queue */ +#define SCHED_POLICY_RR 0x01U /* Round robin */ + +typedef uint8_t sched_policy_t; + +/* Might be set by kconf(1) */ +#if defined(__SCHED_NQUEUE) +#define SCHED_NQUEUE __SCHED_NQUEUE +#else +#define SCHED_NQUEUE 4 +#endif /* __SCHED_NQUEUE */ + +/* Ensure SCHED_NQUEUE is an acceptable value */ +__static_assert(SCHED_NQUEUE <= 8, "SCHED_NQUEUE exceeds max"); +__static_assert(SCHED_NQUEUE > 0, "SCHED_NQUEUE cannot be zero"); + +struct sched_queue { + TAILQ_HEAD(, proc) q; + size_t nthread; +}; + +#endif /* _KERNEL */ +#endif /* !_SYS_SCHEDVAR_H_ */ diff --git a/sys/kern/init_main.c b/sys/kern/init_main.c index 94fa8c0..6018dfe 100644 --- a/sys/kern/init_main.c +++ b/sys/kern/init_main.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -51,6 +52,10 @@ main(void) /* Startup the BSP */ cpu_startup(&g_bsp_ci); + /* Start scheduler and bootstrap APs */ + sched_init(); + mp_bootstrap_aps(&g_bsp_ci); + /* Nothing left to do... halt */ cpu_reboot(REBOOT_HALT); __builtin_unreachable(); diff --git a/sys/kern/kern_sched.c b/sys/kern/kern_sched.c new file mode 100644 index 0000000..b79d682 --- /dev/null +++ b/sys/kern/kern_sched.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define pr_trace(fmt, ...) kprintf("ksched: " fmt, ##__VA_ARGS__) + +void sched_switch(struct trapframe *tf); + +static sched_policy_t policy = SCHED_POLICY_RR; + +/* + * Thread ready queues - all threads ready to be + * scheduled should be added to the toplevel queue. + */ +static struct sched_queue qlist[SCHED_NQUEUE]; + +/* + * Perform timer oneshot + */ +static inline void +sched_oneshot(bool now) +{ + struct timer timer; + size_t usec = now ? SHORT_TIMESLICE_USEC : DEFAULT_TIMESLICE_USEC; + tmrr_status_t tmr_status; + + tmr_status = req_timer(TIMER_SCHED, &timer); + __assert(tmr_status == TMRR_SUCCESS); + + timer.oneshot_us(usec); +} + +/* + * Perform a context switch. + * + * TODO + */ +void +sched_switch(struct trapframe *tf) +{ + static struct spinlock lock = {0}; + + spinlock_acquire(&lock); + spinlock_release(&lock); + sched_oneshot(false); +} + +/* + * Main scheduler loop + */ +void +sched_enter(void) +{ + sched_oneshot(false); + for (;;); +} + +void +sched_init(void) +{ + /* Setup the queues */ + for (int i = 0; i < SCHED_NQUEUE; ++i) { + TAILQ_INIT(&qlist[i].q); + } + + pr_trace("Prepared %d queues (policy=0x%x)\n", + SCHED_NQUEUE, policy); +} -- cgit v1.2.3 From f290314f286b70a8f59becedd5f789c21f675b5d Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Thu, 20 Jun 2024 20:35:38 -0400 Subject: kernel/amd64: intr: Add splraise/splx support Signed-off-by: Ian Moffett --- sys/arch/amd64/amd64/intr.c | 63 ++++++++++++++++++++++++++++++++++++++++--- sys/arch/amd64/amd64/lapic.c | 2 +- sys/include/arch/amd64/asm.h | 14 ++++++++++ sys/include/arch/amd64/cpu.h | 1 + sys/include/arch/amd64/intr.h | 19 ++++++++++++- 5 files changed, 93 insertions(+), 6 deletions(-) (limited to 'sys/include/arch/amd64/cpu.h') diff --git a/sys/arch/amd64/amd64/intr.c b/sys/arch/amd64/amd64/intr.c index b841da7..3e3f309 100644 --- a/sys/arch/amd64/amd64/intr.c +++ b/sys/arch/amd64/amd64/intr.c @@ -28,16 +28,71 @@ */ #include +#include +#include +#include #include +#include +#include +#include + +static struct intr_entry *intrs[256] = {0}; + +void +splraise(uint8_t s) +{ + struct cpu_info *ci = this_cpu(); + + if (s < ci->ipl) { + panic("splraise IPL less than current IPL\n"); + } + + amd64_write_cr8(s); + ci->ipl = s; +} + +void +splx(uint8_t s) +{ + struct cpu_info *ci = this_cpu(); + + if (s > ci->ipl) { + panic("splx IPL greater than current IPL\n"); + } + + amd64_write_cr8(s); + ci->ipl = s; +} int -intr_alloc_vector(void) +intr_alloc_vector(const char *name, uint8_t priority) { - static size_t vec = 0x21; + size_t vec = MAX(priority << IPL_SHIFT, 0x20); + struct intr_entry *intr; - if (vec >= 0xFF) { + /* Sanity check */ + if (vec > NELEM(intrs)) { return -1; } - return vec++; + /* + * Try to allocate an interrupt vector. An IPL is made up + * of 4 bits so there can be 16 vectors per IPL. + */ + for (int i = vec; i < vec + 16; ++i) { + if (intrs[i] != NULL) { + continue; + } + + intr = dynalloc(sizeof(*intr)); + if (intr == NULL) { + return -ENOMEM; + } + + intr->priority = priority; + intrs[i] = intr; + return i; + } + + return -1; } diff --git a/sys/arch/amd64/amd64/lapic.c b/sys/arch/amd64/amd64/lapic.c index b7cefd4..896c2bd 100644 --- a/sys/arch/amd64/amd64/lapic.c +++ b/sys/arch/amd64/amd64/lapic.c @@ -317,7 +317,7 @@ lapic_init(void) /* Allocate a vector if needed */ if (lapic_timer_vec == 0) { - lapic_timer_vec = intr_alloc_vector(); + lapic_timer_vec = intr_alloc_vector("lapictmr", IPL_CLOCK); idt_set_desc(lapic_timer_vec, IDT_INT_GATE, ISR(lapic_tmr_isr), IST_SCHED); } diff --git a/sys/include/arch/amd64/asm.h b/sys/include/arch/amd64/asm.h index d7334fe..e85dd87 100644 --- a/sys/include/arch/amd64/asm.h +++ b/sys/include/arch/amd64/asm.h @@ -84,6 +84,20 @@ amd64_write_cr0(uint64_t val) __ASMV("mov %0, %%cr0" :: "r" (val) : "memory"); } +static inline uint64_t +amd64_read_cr8(void) +{ + uint64_t cr8; + __ASMV("mov %%cr8, %0" : "=r" (cr8) :: "memory"); + return cr8; +} + +static inline void +amd64_write_cr8(uint64_t val) +{ + __ASMV("mov %0, %%cr8" :: "r" (val) : "memory"); +} + static inline uint64_t amd64_read_cr4(void) { diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h index b5420a6..16936e9 100644 --- a/sys/include/arch/amd64/cpu.h +++ b/sys/include/arch/amd64/cpu.h @@ -38,6 +38,7 @@ struct cpu_info { uint32_t apicid; uint8_t has_x2apic : 1; + uint8_t ipl; size_t lapic_tmr_freq; struct tss_entry *tss; struct proc *curtd; diff --git a/sys/include/arch/amd64/intr.h b/sys/include/arch/amd64/intr.h index 3f0da77..af5edf2 100644 --- a/sys/include/arch/amd64/intr.h +++ b/sys/include/arch/amd64/intr.h @@ -36,6 +36,23 @@ #define IST_HW_IRQ 2U #define IST_SW_INT 3U -int intr_alloc_vector(void); +/* Upper 4 bits of interrupt vector */ +#define IPL_SHIFT 4 + +/* + * Interrupt priority levels + */ +#define IPL_NONE 0 /* Don't defer anything */ +#define IPL_BIO 1 /* Block I/O */ +#define IPL_CLOCK 2 /* Clock */ +#define IPL_HIGH 3 /* Defer everything */ + +struct intr_entry { + int priority; +}; + +int intr_alloc_vector(const char *name, uint8_t priority); +void splraise(uint8_t s); +void splx(uint8_t s); #endif -- cgit v1.2.3