From de478dd99768b8b6bb67438254ca2c06db241cf7 Mon Sep 17 00:00:00 2001 From: sigsegv7 Date: Thu, 14 Sep 2023 03:38:52 -0400 Subject: kernel/amd64: Add I/O APIC pin mask/unmask logic Signed-off-by: sigsegv7 --- sys/arch/amd64/ioapic.c | 52 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 48 insertions(+), 4 deletions(-) (limited to 'sys/arch') diff --git a/sys/arch/amd64/ioapic.c b/sys/arch/amd64/ioapic.c index 70a9114..cc232cf 100644 --- a/sys/arch/amd64/ioapic.c +++ b/sys/arch/amd64/ioapic.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -99,6 +100,52 @@ ioapic_write_redentry(const union ioapic_redentry *entry, uint8_t index) ioapic_writel(IOREDTBL + index * 2 + 1, (uint32_t)(entry->value >> 32)); } +/* + * Mask I/O APIC pin with "raw" pin number + * (Global System Interrupt) + */ +void +ioapic_gsi_mask(uint8_t gsi) +{ + union ioapic_redentry redentry; + + ioapic_read_redentry(&redentry, gsi); + redentry.interrupt_mask = 1; + ioapic_write_redentry(&redentry, gsi); +} + +/* + * Unmask I/O APIC pin with "raw" pin number + * (Global System Interrupt) + */ +void +ioapic_gsi_unmask(uint8_t gsi) +{ + union ioapic_redentry redentry; + + ioapic_read_redentry(&redentry, gsi); + redentry.interrupt_mask = 0; + ioapic_write_redentry(&redentry, gsi); +} + +void +ioapic_irq_mask(uint8_t irq) +{ + uint8_t gsi; + + gsi = irq_to_gsi(irq); + ioapic_gsi_mask(gsi); +} + +void +ioapic_irq_unmask(uint8_t irq) +{ + uint8_t gsi; + + gsi = irq_to_gsi(irq); + ioapic_gsi_unmask(gsi); +} + void ioapic_set_base(void *mmio_base) { @@ -111,7 +158,6 @@ ioapic_init(void) { size_t tmp; uint8_t redir_entry_cnt; - union ioapic_redentry redir_entry; /* Sanity check */ if (ioapic_base == NULL) @@ -123,8 +169,6 @@ ioapic_init(void) KINFO("Masking %d GSIs...\n", redir_entry_cnt); for (uint8_t i = 0; i < redir_entry_cnt; ++i) { - ioapic_read_redentry(&redir_entry, i); - redir_entry.interrupt_mask = 1; - ioapic_write_redentry(&redir_entry, i); + ioapic_gsi_mask(i); } } -- cgit v1.2.3