From b184afe98009836e31f2daa7dcb5fba211c453e1 Mon Sep 17 00:00:00 2001 From: sigsegv7 Date: Wed, 18 Oct 2023 18:22:48 -0400 Subject: kernel/amd64: lapic: Add ESR reading logic Signed-off-by: sigsegv7 --- sys/arch/amd64/lapic.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'sys/arch/amd64') diff --git a/sys/arch/amd64/lapic.c b/sys/arch/amd64/lapic.c index af219d2..6f2f6c1 100644 --- a/sys/arch/amd64/lapic.c +++ b/sys/arch/amd64/lapic.c @@ -208,6 +208,27 @@ lapic_set_ldr(void) lapic_writel(LAPIC_LDR, LAPIC_STARTUP_LID); } +/* + * Reads the Local APIC error status + * register. Returns the value read. + * + * XXX: It is a good idea to save the value returned as + * each read will clear the register. + */ +static inline uint32_t +lapic_read_esr(void) +{ + /* + * We'll need to write 0 to clear the ESR and reload + * it with any new errors that happened... In xAPIC mode + * we can write anything to do this; however, in x2APIC + * mode, writes of 0 are enforced. We'll only write 0 to + * work both with x2APIC and xAPIC mode... + */ + lapic_writel(LAPIC_ERR, 0); + return lapic_readl(LAPIC_ERR); +} + void lapic_timer_init(size_t *freq_out) { -- cgit v1.2.3