From b6cceb40835d6b200aaf8731ba9dac5c3bb62180 Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Tue, 17 Dec 2024 21:40:34 -0500 Subject: kernel/amd64: pci: Allow mapping of 64 bit BARs Signed-off-by: Ian Moffett --- sys/arch/amd64/pci/pci_machdep.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'sys/arch/amd64/pci') diff --git a/sys/arch/amd64/pci/pci_machdep.c b/sys/arch/amd64/pci/pci_machdep.c index ea34b25..1cc2162 100644 --- a/sys/arch/amd64/pci/pci_machdep.c +++ b/sys/arch/amd64/pci/pci_machdep.c @@ -103,7 +103,7 @@ int pci_map_bar(struct pci_device *dev, uint8_t barno, void **vap) { uint8_t barreg = pci_get_barreg(dev, barno); - uintptr_t tmp, bar; + uintptr_t tmp, tmp1, bar; uint32_t size; if (barreg == 0) @@ -122,7 +122,21 @@ pci_map_bar(struct pci_device *dev, uint8_t barno, void **vap) /* Restore old value and map the BAR */ pci_writel(dev, barreg, tmp); - bar = dev->bar[barno] & PCI_BAR_MEMMASK; + + /* + * We'll only need to worry about using one BAR + * if the device has a 32-bit MMIO space. However, + * with 64-bit MMIO spaces, two BARs are used. + */ + if (PCI_BAR_32(dev->bar[barno])) { + bar = dev->bar[barno] & PCI_BAR_MEMMASK; + } else { + /* Assume 64-bit */ + tmp = dev->bar[barno] & PCI_BAR_MEMMASK; + tmp1 = dev->bar[barno + 1] & PCI_BAR_MEMMASK; + bar = COMBINE32(tmp1, tmp); + } + return bus_map(bar, size, 0, vap); } -- cgit v1.2.3