From 98ccb3a2d41015b42d46d8b382decc755a003c3f Mon Sep 17 00:00:00 2001
From: Ian Moffett <ian@osmora.org>
Date: Tue, 4 Jun 2024 13:41:11 -0400
Subject: project: Initial commit

Signed-off-by: Ian Moffett <ian@osmora.org>
---
 sys/arch/amd64/conf/GENERIC |  1 +
 sys/arch/amd64/conf/link.ld | 47 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)
 create mode 100644 sys/arch/amd64/conf/GENERIC
 create mode 100644 sys/arch/amd64/conf/link.ld

(limited to 'sys/arch/amd64/conf')

diff --git a/sys/arch/amd64/conf/GENERIC b/sys/arch/amd64/conf/GENERIC
new file mode 100644
index 0000000..70b786d
--- /dev/null
+++ b/sys/arch/amd64/conf/GENERIC
@@ -0,0 +1 @@
+// TODO
diff --git a/sys/arch/amd64/conf/link.ld b/sys/arch/amd64/conf/link.ld
new file mode 100644
index 0000000..b073054
--- /dev/null
+++ b/sys/arch/amd64/conf/link.ld
@@ -0,0 +1,47 @@
+OUTPUT_FORMAT(elf64-x86-64)
+OUTPUT_ARCH(i386:x86-64)
+ENTRY(main)
+
+PHDRS
+{
+    text          PT_LOAD    FLAGS((1 << 0) | (1 << 2)) ; /* Execute + Read */
+    rodata        PT_LOAD    FLAGS((1 << 2)) ;            /* Read only */
+    data          PT_LOAD    FLAGS((1 << 1) | (1 << 2)) ; /* Write + Read */
+}
+
+SECTIONS
+{
+    . = 0xFFFFFFFF80000000;
+
+    .text : {
+        *(.text .text.*)
+    } :text
+
+    . += CONSTANT(MAXPAGESIZE);
+
+    .rodata : {
+        *(.rodata .rodata.*)
+    } :rodata
+
+    .drivers : {
+        __drivers_init_start = .;
+        *(.drivers .drivers)
+        __drivers_init_end = .;
+    } :rodata
+
+    . += CONSTANT(MAXPAGESIZE);
+
+    .data : {
+        *(.data .data.*)
+    } :data
+
+    .bss : {
+        *(COMMON)
+        *(.bss .bss.*)
+    } :data
+
+    /DISCARD/ : {
+        *(.eh_frame)
+        *(.note .note.*)
+    }
+}
-- 
cgit v1.2.3


From 955d6a381f53c234ce1f4d52aa57f183ed9a6e65 Mon Sep 17 00:00:00 2001
From: Ian Moffett <ian@osmora.org>
Date: Tue, 4 Jun 2024 22:13:30 -0400
Subject: kernel/amd64: Support IBRS

Signed-off-by: Ian Moffett <ian@osmora.org>
---
 sys/arch/amd64/amd64/machdep.c | 19 +++++++++++++++
 sys/arch/amd64/amd64/spectre.S | 53 ++++++++++++++++++++++++++++++++++++++++++
 sys/arch/amd64/conf/GENERIC    |  3 ++-
 sys/include/arch/amd64/msr.h   |  2 ++
 4 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 sys/arch/amd64/amd64/spectre.S

(limited to 'sys/arch/amd64/conf')

diff --git a/sys/arch/amd64/amd64/machdep.c b/sys/arch/amd64/amd64/machdep.c
index 19ba28a..275c23e 100644
--- a/sys/arch/amd64/amd64/machdep.c
+++ b/sys/arch/amd64/amd64/machdep.c
@@ -35,6 +35,14 @@
 #include <machine/asm.h>
 #include <machine/cpuid.h>
 
+#if defined(__SPECTRE_IBRS)
+#define SPECTRE_IBRS  __SPECTRE_IBRS
+#else
+#define SPECTRE_IBRS 0
+#endif
+
+int ibrs_enable(void);
+
 static struct cpu_info g_bsp_ci = {0};
 static struct gdtr bsp_gdtr = {
     .limit = sizeof(struct gdt_entry) * 256 - 1,
@@ -58,6 +66,16 @@ setup_vectors(void)
     idt_set_desc(0xE, IDT_TRAP_GATE, ISR(page_fault), 0);
 }
 
+static void
+try_mitigate_spectre(void)
+{
+    if (!SPECTRE_IBRS) {
+        return;
+    }
+
+    ibrs_enable();
+}
+
 void
 cpu_startup(void)
 {
@@ -66,4 +84,5 @@ cpu_startup(void)
 
     setup_vectors();
     amd64_write_gs_base((uintptr_t)&g_bsp_ci);
+    try_mitigate_spectre();
 }
diff --git a/sys/arch/amd64/amd64/spectre.S b/sys/arch/amd64/amd64/spectre.S
new file mode 100644
index 0000000..6781cbd
--- /dev/null
+++ b/sys/arch/amd64/amd64/spectre.S
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ #include <machine/msr.h>
+
+    .text
+    .globl ibrs_enable
+    .type ibrs_enable, @function
+ibrs_enable:
+    /* See if it is supported */
+    mov $7, %eax
+    xor %ecx, %ecx
+    cpuid
+    bt $26, %edx
+    jnc fail
+
+    /* Now we enable it */
+    mov $IA32_SPEC_CTL, %ecx
+    rdmsr
+    or $1, %eax
+    wrmsr
+    xor %rax, %rax
+    jmp 1f
+fail:
+    mov $1, %rax
+1:
+    retq
diff --git a/sys/arch/amd64/conf/GENERIC b/sys/arch/amd64/conf/GENERIC
index 70b786d..1a48a94 100644
--- a/sys/arch/amd64/conf/GENERIC
+++ b/sys/arch/amd64/conf/GENERIC
@@ -1 +1,2 @@
-// TODO
+// Kernel options
+option SPECTRE_IBRS yes
diff --git a/sys/include/arch/amd64/msr.h b/sys/include/arch/amd64/msr.h
index bc0dbcb..6ad95f1 100644
--- a/sys/include/arch/amd64/msr.h
+++ b/sys/include/arch/amd64/msr.h
@@ -33,6 +33,7 @@
 #define IA32_SPEC_CTL       0x00000048
 #define IA32_KERNEL_GS_BASE 0xC0000102
 
+#if !defined(__ASSEMBLER__)
 static inline uint64_t
 rdmsr(uint32_t msr_addr)
 {
@@ -60,4 +61,5 @@ wrmsr(uint32_t msr_addr, uint64_t value)
     );
 }
 
+#endif  /* !__ASSEMBLER__ */
 #endif  /* !_MACHINE_MSR_H_ */
-- 
cgit v1.2.3


From 433d6e282c9f1455fef07333807424f4bd07878e Mon Sep 17 00:00:00 2001
From: Ian Moffett <ian@osmora.org>
Date: Tue, 4 Jun 2024 23:28:15 -0400
Subject: kernel/amd64: spectre: Disable IBRS by default

Signed-off-by: Ian Moffett <ian@osmora.org>
---
 sys/arch/amd64/conf/GENERIC | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'sys/arch/amd64/conf')

diff --git a/sys/arch/amd64/conf/GENERIC b/sys/arch/amd64/conf/GENERIC
index 1a48a94..ea6ba76 100644
--- a/sys/arch/amd64/conf/GENERIC
+++ b/sys/arch/amd64/conf/GENERIC
@@ -1,2 +1,2 @@
 // Kernel options
-option SPECTRE_IBRS yes
+option SPECTRE_IBRS no
-- 
cgit v1.2.3


From f8ce8234aa7247c8f3a4317f5671b5fd40ffb8c8 Mon Sep 17 00:00:00 2001
From: Ian Moffett <ian@osmora.org>
Date: Fri, 7 Jun 2024 21:25:10 -0400
Subject: kernel: Add __cacheline_aligned macro

This commit introduces a "__cacheline_aligned" macro which aligns data
by the cache line size (COHERENCY_UNIT bytes). This is useful for
heavily contended locks.

Signed-off-by: Ian Moffett <ian@osmora.org>
---
 sys/arch/amd64/conf/link.ld |  8 +++++++-
 sys/include/sys/cdefs.h     | 17 +++++++++++++++++
 sys/include/sys/param.h     |  5 +++++
 3 files changed, 29 insertions(+), 1 deletion(-)

(limited to 'sys/arch/amd64/conf')

diff --git a/sys/arch/amd64/conf/link.ld b/sys/arch/amd64/conf/link.ld
index b073054..9c47a81 100644
--- a/sys/arch/amd64/conf/link.ld
+++ b/sys/arch/amd64/conf/link.ld
@@ -32,7 +32,7 @@ SECTIONS
     . += CONSTANT(MAXPAGESIZE);
 
     .data : {
-        *(.data .data.*)
+        *(.data)
     } :data
 
     .bss : {
@@ -40,6 +40,12 @@ SECTIONS
         *(.bss .bss.*)
     } :data
 
+    /* -- Cache line alignment -- */
+    . = ALIGN(64);
+    .data.cacheline_aligned : {
+        *(.data.cacheline_aligned)
+    }
+
     /DISCARD/ : {
         *(.eh_frame)
         *(.note .note.*)
diff --git a/sys/include/sys/cdefs.h b/sys/include/sys/cdefs.h
index fc21750..655a023 100644
--- a/sys/include/sys/cdefs.h
+++ b/sys/include/sys/cdefs.h
@@ -30,10 +30,27 @@
 #ifndef _SYS_CDEFS_H_
 #define _SYS_CDEFS_H_
 
+#include <sys/param.h>
+
 #define __ASMV          __asm__ __volatile__
 #define __always_inline __attribute__((__always_inline__))
 #define __packed        __attribute__((__packed__))
 #define __likely(exp)   __builtin_expect(((exp) != 0), 1)
 #define __unlikely(exp) __builtin_expect(((exp) != 0), 0)
 
+#if defined(_KERNEL)
+/*
+ *  Align data on a cache line boundary. This is
+ *  mostly useful for certain locks to ensure they
+ *  have their own cache line to reduce contention.
+ *
+ */
+#ifndef __cacheline_aligned
+#define __cacheline_aligned                             \
+    __attribute__((__aligned__(COHERENCY_UNIT),         \
+                __section__(".data.cacheline_aligned")))
+
+#endif  /* __cacheline_aligned */
+#endif  /* _KERNEL */
+
 #endif  /* !_SYS_CDEFS_H_ */
diff --git a/sys/include/sys/param.h b/sys/include/sys/param.h
index a35a094..483dc15 100644
--- a/sys/include/sys/param.h
+++ b/sys/include/sys/param.h
@@ -30,6 +30,11 @@
 #ifndef _SYS_PARAM_H_
 #define _SYS_PARAM_H_
 
+/* Assumed cache line size */
+#ifndef COHERENCY_UNIT
+#define COHERENCY_UNIT 64
+#endif
+
 /* Bit related macros */
 #define ISSET(v, f)  ((v) & (f))
 #define BIT(n) (1 << (n))
-- 
cgit v1.2.3


From 55845113211400c9b1657ec3ce72b06a05efac4e Mon Sep 17 00:00:00 2001
From: Ian Moffett <ian@osmora.org>
Date: Sat, 8 Jun 2024 18:19:51 -0400
Subject: kernel/amd64: Prepare for scheduler

Signed-off-by: Ian Moffett <ian@osmora.org>
---
 sys/arch/amd64/amd64/lapic_intr.S |   2 +
 sys/arch/amd64/amd64/mp.c         |  93 ++++++++++++++++++++++++++++++++++
 sys/arch/amd64/conf/GENERIC       |   3 ++
 sys/include/arch/amd64/cpu.h      |   4 ++
 sys/include/sys/proc.h            |  48 ++++++++++++++++++
 sys/include/sys/sched.h           |  39 +++++++++++++++
 sys/include/sys/schedvar.h        |  63 +++++++++++++++++++++++
 sys/kern/init_main.c              |   5 ++
 sys/kern/kern_sched.c             | 102 ++++++++++++++++++++++++++++++++++++++
 9 files changed, 359 insertions(+)
 create mode 100644 sys/arch/amd64/amd64/mp.c
 create mode 100644 sys/include/sys/proc.h
 create mode 100644 sys/include/sys/sched.h
 create mode 100644 sys/include/sys/schedvar.h
 create mode 100644 sys/kern/kern_sched.c

(limited to 'sys/arch/amd64/conf')

diff --git a/sys/arch/amd64/amd64/lapic_intr.S b/sys/arch/amd64/amd64/lapic_intr.S
index 295de2d..a3fa7e4 100644
--- a/sys/arch/amd64/amd64/lapic_intr.S
+++ b/sys/arch/amd64/amd64/lapic_intr.S
@@ -5,5 +5,7 @@
 lapic_tmr_isr:
     push_trapframe $0
     mov %rsp, %rdi
+    call sched_switch
+    call lapic_eoi
     pop_trapframe
     iretq
diff --git a/sys/arch/amd64/amd64/mp.c b/sys/arch/amd64/amd64/mp.c
new file mode 100644
index 0000000..9512aa6
--- /dev/null
+++ b/sys/arch/amd64/amd64/mp.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <sys/limine.h>
+#include <sys/syslog.h>
+#include <sys/spinlock.h>
+#include <sys/sched.h>
+#include <machine/cpu.h>
+#include <vm/dynalloc.h>
+#include <assert.h>
+#include <string.h>
+
+#define pr_trace(fmt, ...) kprintf("cpu_mp: " fmt, ##__VA_ARGS__)
+
+static volatile struct limine_smp_request g_smp_req = {
+    .id = LIMINE_SMP_REQUEST,
+    .revision = 0
+};
+
+static void
+ap_trampoline(struct limine_smp_info *si)
+{
+    struct spinlock lock = {0};
+    struct cpu_info *ci;
+
+    spinlock_acquire(&lock);
+    ci = dynalloc(sizeof(*ci));
+    __assert(ci != NULL);
+
+    memset(ci, 0, sizeof(*ci));
+    cpu_startup(ci);
+
+    spinlock_release(&lock);
+    sched_enter();
+
+    while (1);
+}
+
+void
+mp_bootstrap_aps(struct cpu_info *ci)
+{
+    struct limine_smp_response *resp = g_smp_req.response;
+    struct limine_smp_info **cpus;
+    size_t cpu_init_counter;
+
+    /* Should not happen */
+    __assert(resp != NULL);
+
+    cpus = resp->cpus;
+    cpu_init_counter = resp->cpu_count - 1;
+
+    if (resp->cpu_count == 1) {
+        pr_trace("CPU has 1 core, no APs to bootstrap...\n");
+        return;
+    }
+
+    pr_trace("Bootstrapping %d cores...\n", cpu_init_counter);
+    for (size_t i = 0; i < resp->cpu_count; ++i) {
+        if (ci->apicid == cpus[i]->lapic_id) {
+            pr_trace("Skip %d (BSP)... continue\n", ci->apicid);
+            continue;
+        }
+
+        cpus[i]->goto_address = ap_trampoline;
+    }
+}
diff --git a/sys/arch/amd64/conf/GENERIC b/sys/arch/amd64/conf/GENERIC
index ea6ba76..a7bbc81 100644
--- a/sys/arch/amd64/conf/GENERIC
+++ b/sys/arch/amd64/conf/GENERIC
@@ -1,2 +1,5 @@
 // Kernel options
 option SPECTRE_IBRS no
+
+// Kernel constants
+setval SCHED_NQUEUE 4
diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h
index 84391ba..b5420a6 100644
--- a/sys/include/arch/amd64/cpu.h
+++ b/sys/include/arch/amd64/cpu.h
@@ -32,6 +32,7 @@
 
 #include <sys/types.h>
 #include <sys/cdefs.h>
+#include <sys/proc.h>
 #include <machine/tss.h>
 
 struct cpu_info {
@@ -39,10 +40,13 @@ struct cpu_info {
     uint8_t has_x2apic : 1;
     size_t lapic_tmr_freq;
     struct tss_entry *tss;
+    struct proc *curtd;
 };
 
 void cpu_startup(struct cpu_info *ci);
 struct cpu_info *this_cpu(void);
+void mp_bootstrap_aps(struct cpu_info *ci);
+
 extern struct cpu_info g_bsp_ci;
 
 #endif  /* !_MACHINE_CPU_H_ */
diff --git a/sys/include/sys/proc.h b/sys/include/sys/proc.h
new file mode 100644
index 0000000..ba47a5c
--- /dev/null
+++ b/sys/include/sys/proc.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SYS_PROC_H_
+#define _SYS_PROC_H_
+
+#include <sys/types.h>
+#include <sys/spinlock.h>
+#if defined(_KERNEL)
+#include <machine/cpu.h>
+#include <machine/frame.h>
+#endif  /* _KERNEL */
+
+#if defined(_KERNEL)
+
+struct proc {
+    pid_t pid;
+    struct cpu_info *cpu;
+};
+
+#endif  /* _KERNEL */
+#endif  /* !_SYS_PROC_H_ */
diff --git a/sys/include/sys/sched.h b/sys/include/sys/sched.h
new file mode 100644
index 0000000..33d546d
--- /dev/null
+++ b/sys/include/sys/sched.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SYS_SCHED_H_
+#define _SYS_SCHED_H_
+
+#if defined(_KERNEL)
+
+void sched_init(void);
+void sched_enter(void);
+
+#endif  /* _KERNEL */
+#endif  /* !_SYS_SCHED_H_ */
diff --git a/sys/include/sys/schedvar.h b/sys/include/sys/schedvar.h
new file mode 100644
index 0000000..00caeb4
--- /dev/null
+++ b/sys/include/sys/schedvar.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SYS_SCHEDVAR_H_
+#define _SYS_SCHEDVAR_H_
+
+#include <sys/cdefs.h>
+#include <sys/queue.h>
+#include <sys/proc.h>
+
+#if defined(_KERNEL)
+#define DEFAULT_TIMESLICE_USEC 1050
+#define SHORT_TIMESLICE_USEC 10
+
+#define SCHED_POLICY_MLFQ 0x00U   /* Multilevel feedback queue */
+#define SCHED_POLICY_RR   0x01U   /* Round robin */
+
+typedef uint8_t sched_policy_t;
+
+/* Might be set by kconf(1) */
+#if defined(__SCHED_NQUEUE)
+#define SCHED_NQUEUE __SCHED_NQUEUE
+#else
+#define SCHED_NQUEUE 4
+#endif  /* __SCHED_NQUEUE */
+
+/* Ensure SCHED_NQUEUE is an acceptable value */
+__static_assert(SCHED_NQUEUE <= 8, "SCHED_NQUEUE exceeds max");
+__static_assert(SCHED_NQUEUE > 0, "SCHED_NQUEUE cannot be zero");
+
+struct sched_queue {
+    TAILQ_HEAD(, proc) q;
+    size_t nthread;
+};
+
+#endif  /* _KERNEL */
+#endif  /* !_SYS_SCHEDVAR_H_ */
diff --git a/sys/kern/init_main.c b/sys/kern/init_main.c
index 94fa8c0..6018dfe 100644
--- a/sys/kern/init_main.c
+++ b/sys/kern/init_main.c
@@ -29,6 +29,7 @@
 
 #include <sys/reboot.h>
 #include <sys/syslog.h>
+#include <sys/sched.h>
 #include <dev/cons/cons.h>
 #include <dev/acpi/acpi.h>
 #include <machine/cpu.h>
@@ -51,6 +52,10 @@ main(void)
     /* Startup the BSP */
     cpu_startup(&g_bsp_ci);
 
+    /* Start scheduler and bootstrap APs */
+    sched_init();
+    mp_bootstrap_aps(&g_bsp_ci);
+
     /* Nothing left to do... halt */
     cpu_reboot(REBOOT_HALT);
     __builtin_unreachable();
diff --git a/sys/kern/kern_sched.c b/sys/kern/kern_sched.c
new file mode 100644
index 0000000..b79d682
--- /dev/null
+++ b/sys/kern/kern_sched.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <sys/sched.h>
+#include <sys/schedvar.h>
+#include <sys/cdefs.h>
+#include <sys/syslog.h>
+#include <machine/frame.h>
+#include <dev/timer.h>
+#include <assert.h>
+
+#define pr_trace(fmt, ...) kprintf("ksched: " fmt, ##__VA_ARGS__)
+
+void sched_switch(struct trapframe *tf);
+
+static sched_policy_t policy = SCHED_POLICY_RR;
+
+/*
+ * Thread ready queues - all threads ready to be
+ * scheduled should be added to the toplevel queue.
+ */
+static struct sched_queue qlist[SCHED_NQUEUE];
+
+/*
+ * Perform timer oneshot
+ */
+static inline void
+sched_oneshot(bool now)
+{
+    struct timer timer;
+    size_t usec = now ? SHORT_TIMESLICE_USEC : DEFAULT_TIMESLICE_USEC;
+    tmrr_status_t tmr_status;
+
+    tmr_status = req_timer(TIMER_SCHED, &timer);
+    __assert(tmr_status == TMRR_SUCCESS);
+
+    timer.oneshot_us(usec);
+}
+
+/*
+ * Perform a context switch.
+ *
+ * TODO
+ */
+void
+sched_switch(struct trapframe *tf)
+{
+    static struct spinlock lock = {0};
+
+    spinlock_acquire(&lock);
+    spinlock_release(&lock);
+    sched_oneshot(false);
+}
+
+/*
+ * Main scheduler loop
+ */
+void
+sched_enter(void)
+{
+    sched_oneshot(false);
+    for (;;);
+}
+
+void
+sched_init(void)
+{
+    /* Setup the queues */
+    for (int i = 0; i < SCHED_NQUEUE; ++i) {
+        TAILQ_INIT(&qlist[i].q);
+    }
+
+    pr_trace("Prepared %d queues (policy=0x%x)\n",
+        SCHED_NQUEUE, policy);
+}
-- 
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