From e1b4932b5a133351e9d4aefee9c9f7280f86412f Mon Sep 17 00:00:00 2001 From: Ian Moffett Date: Wed, 13 Aug 2025 00:06:02 -0400 Subject: kernel/amd64: cpu: Add detection of invariant TSC This commit introduces the 'CPU_FEAT_TSCINV' feature bit to indicate whether or not the CPU supports an invariant TSC. Signed-off-by: Ian Moffett --- sys/arch/amd64/amd64/machdep.c | 10 +++++++++- sys/include/arch/amd64/cpu.h | 7 ++++--- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/sys/arch/amd64/amd64/machdep.c b/sys/arch/amd64/amd64/machdep.c index 6408ad3..3338caa 100644 --- a/sys/arch/amd64/amd64/machdep.c +++ b/sys/arch/amd64/amd64/machdep.c @@ -306,7 +306,7 @@ cpu_get_vendor(struct cpu_info *ci) static void cpu_get_info(struct cpu_info *ci) { - uint32_t eax, ebx, ecx, unused; + uint32_t unused, eax, ebx, ecx, edx; uint8_t ext_model, ext_family; /* Get the vendor information */ @@ -321,6 +321,14 @@ cpu_get_info(struct cpu_info *ci) if (ISSET(ecx, BIT(2))) ci->feat |= CPU_FEAT_UMIP; + /* + * Processor power management information bits as well + * as bits describing RAS capabilities + */ + CPUID(0x80000007, unused, unused, unused, edx); + if (ISSET(edx, BIT(8))) + ci->feat |= CPU_FEAT_TSCINV; + /* * Processor info and feature bits */ diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h index 3dadebd..6ed675e 100644 --- a/sys/include/arch/amd64/cpu.h +++ b/sys/include/arch/amd64/cpu.h @@ -42,9 +42,10 @@ #define CPU_IRQ(IRQ_N) (BIT((IRQ_N)) & 0xFF) /* Feature bits */ -#define CPU_FEAT_SMAP BIT(0) -#define CPU_FEAT_SMEP BIT(1) -#define CPU_FEAT_UMIP BIT(2) +#define CPU_FEAT_SMAP BIT(0) +#define CPU_FEAT_SMEP BIT(1) +#define CPU_FEAT_UMIP BIT(2) +#define CPU_FEAT_TSCINV BIT(3) /* TSC invariant */ /* CPU vendors */ #define CPU_VENDOR_OTHER 0x00000000 -- cgit v1.2.3