diff options
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/amd64/amd64/intr.c | 7 | ||||
| -rw-r--r-- | sys/arch/amd64/amd64/vector.S | 126 |
2 files changed, 67 insertions, 66 deletions
diff --git a/sys/arch/amd64/amd64/intr.c b/sys/arch/amd64/amd64/intr.c index 1529b1c..9f70e88 100644 --- a/sys/arch/amd64/amd64/intr.c +++ b/sys/arch/amd64/amd64/intr.c @@ -96,11 +96,12 @@ intr_register(const char *name, const struct intr_hand *ih) * Try to allocate an interrupt vector. An IPL is made up * of 4 bits so there can be 16 vectors per IPL. * - * XXX: Vector 0x20 is reserved for the Hyra scheduler and - * vector 0x21 is reserved for the CPU halt IPI. + * XXX: Vector 0x20 is reserved for the Hyra scheduler, + * vector 0x21 is reserved for the CPU halt IPI, + * and vector 0x22 is reserved for TLB shootdowns. */ for (int i = vec; i < vec + 16; ++i) { - if (g_intrs[i] != NULL || i < 0x22) { + if (g_intrs[i] != NULL || i < 0x23) { continue; } diff --git a/sys/arch/amd64/amd64/vector.S b/sys/arch/amd64/amd64/vector.S index 32ccd34..d2a3d89 100644 --- a/sys/arch/amd64/amd64/vector.S +++ b/sys/arch/amd64/amd64/vector.S @@ -64,69 +64,69 @@ done: .globl pin_isr_load pin_isr_load: - IDT_SET_VEC 34, ioapic_edge_0 - IDT_SET_VEC 35, ioapic_edge_1 - IDT_SET_VEC 36, ioapic_edge_2 - IDT_SET_VEC 37, ioapic_edge_3 - IDT_SET_VEC 38, ioapic_edge_4 - IDT_SET_VEC 39, ioapic_edge_5 - IDT_SET_VEC 40, ioapic_edge_6 - IDT_SET_VEC 41, ioapic_edge_7 - IDT_SET_VEC 42, ioapic_edge_8 - IDT_SET_VEC 43, ioapic_edge_9 - IDT_SET_VEC 44, ioapic_edge_10 - IDT_SET_VEC 45, ioapic_edge_11 - IDT_SET_VEC 46, ioapic_edge_12 - IDT_SET_VEC 47, ioapic_edge_13 - IDT_SET_VEC 48, ioapic_edge_14 - IDT_SET_VEC 49, ioapic_edge_15 - IDT_SET_VEC 50, ioapic_edge_16 - IDT_SET_VEC 51, ioapic_edge_17 - IDT_SET_VEC 52, ioapic_edge_18 - IDT_SET_VEC 53, ioapic_edge_19 - IDT_SET_VEC 54, ioapic_edge_20 - IDT_SET_VEC 55, ioapic_edge_21 - IDT_SET_VEC 56, ioapic_edge_22 - IDT_SET_VEC 57, ioapic_edge_23 - IDT_SET_VEC 58, ioapic_edge_24 - IDT_SET_VEC 59, ioapic_edge_25 - IDT_SET_VEC 60, ioapic_edge_26 - IDT_SET_VEC 61, ioapic_edge_27 - IDT_SET_VEC 62, ioapic_edge_28 - IDT_SET_VEC 63, ioapic_edge_29 - IDT_SET_VEC 64, ioapic_edge_30 - IDT_SET_VEC 65, ioapic_edge_31 - IDT_SET_VEC 66, ioapic_edge_32 - IDT_SET_VEC 67, ioapic_edge_33 - IDT_SET_VEC 68, ioapic_edge_34 - IDT_SET_VEC 69, ioapic_edge_35 - IDT_SET_VEC 70, ioapic_edge_36 - IDT_SET_VEC 71, ioapic_edge_37 - IDT_SET_VEC 72, ioapic_edge_38 - IDT_SET_VEC 73, ioapic_edge_39 - IDT_SET_VEC 74, ioapic_edge_40 - IDT_SET_VEC 75, ioapic_edge_41 - IDT_SET_VEC 76, ioapic_edge_42 - IDT_SET_VEC 77, ioapic_edge_43 - IDT_SET_VEC 78, ioapic_edge_44 - IDT_SET_VEC 79, ioapic_edge_45 - IDT_SET_VEC 80, ioapic_edge_46 - IDT_SET_VEC 81, ioapic_edge_47 - IDT_SET_VEC 82, ioapic_edge_48 - IDT_SET_VEC 83, ioapic_edge_49 - IDT_SET_VEC 84, ioapic_edge_50 - IDT_SET_VEC 85, ioapic_edge_51 - IDT_SET_VEC 86, ioapic_edge_52 - IDT_SET_VEC 87, ioapic_edge_53 - IDT_SET_VEC 88, ioapic_edge_54 - IDT_SET_VEC 89, ioapic_edge_55 - IDT_SET_VEC 90, ioapic_edge_56 - IDT_SET_VEC 91, ioapic_edge_57 - IDT_SET_VEC 92, ioapic_edge_58 - IDT_SET_VEC 93, ioapic_edge_59 - IDT_SET_VEC 94, ioapic_edge_60 - IDT_SET_VEC 95, ioapic_edge_61 - IDT_SET_VEC 96, ioapic_edge_62 + IDT_SET_VEC 35, ioapic_edge_0 + IDT_SET_VEC 36, ioapic_edge_1 + IDT_SET_VEC 37, ioapic_edge_2 + IDT_SET_VEC 38, ioapic_edge_3 + IDT_SET_VEC 39, ioapic_edge_4 + IDT_SET_VEC 40, ioapic_edge_5 + IDT_SET_VEC 41, ioapic_edge_6 + IDT_SET_VEC 42, ioapic_edge_7 + IDT_SET_VEC 43, ioapic_edge_8 + IDT_SET_VEC 44, ioapic_edge_9 + IDT_SET_VEC 45, ioapic_edge_10 + IDT_SET_VEC 46, ioapic_edge_11 + IDT_SET_VEC 47, ioapic_edge_12 + IDT_SET_VEC 48, ioapic_edge_13 + IDT_SET_VEC 49, ioapic_edge_14 + IDT_SET_VEC 50, ioapic_edge_15 + IDT_SET_VEC 51, ioapic_edge_16 + IDT_SET_VEC 52, ioapic_edge_17 + IDT_SET_VEC 53, ioapic_edge_18 + IDT_SET_VEC 54, ioapic_edge_19 + IDT_SET_VEC 55, ioapic_edge_20 + IDT_SET_VEC 56, ioapic_edge_21 + IDT_SET_VEC 57, ioapic_edge_22 + IDT_SET_VEC 58, ioapic_edge_23 + IDT_SET_VEC 59, ioapic_edge_24 + IDT_SET_VEC 60, ioapic_edge_25 + IDT_SET_VEC 61, ioapic_edge_26 + IDT_SET_VEC 62, ioapic_edge_27 + IDT_SET_VEC 63, ioapic_edge_28 + IDT_SET_VEC 64, ioapic_edge_29 + IDT_SET_VEC 65, ioapic_edge_30 + IDT_SET_VEC 66, ioapic_edge_31 + IDT_SET_VEC 67, ioapic_edge_32 + IDT_SET_VEC 68, ioapic_edge_33 + IDT_SET_VEC 69, ioapic_edge_34 + IDT_SET_VEC 70, ioapic_edge_35 + IDT_SET_VEC 71, ioapic_edge_36 + IDT_SET_VEC 72, ioapic_edge_37 + IDT_SET_VEC 73, ioapic_edge_38 + IDT_SET_VEC 74, ioapic_edge_39 + IDT_SET_VEC 75, ioapic_edge_40 + IDT_SET_VEC 76, ioapic_edge_41 + IDT_SET_VEC 77, ioapic_edge_42 + IDT_SET_VEC 78, ioapic_edge_43 + IDT_SET_VEC 79, ioapic_edge_44 + IDT_SET_VEC 80, ioapic_edge_45 + IDT_SET_VEC 81, ioapic_edge_46 + IDT_SET_VEC 82, ioapic_edge_47 + IDT_SET_VEC 83, ioapic_edge_48 + IDT_SET_VEC 84, ioapic_edge_49 + IDT_SET_VEC 85, ioapic_edge_50 + IDT_SET_VEC 86, ioapic_edge_51 + IDT_SET_VEC 87, ioapic_edge_52 + IDT_SET_VEC 88, ioapic_edge_53 + IDT_SET_VEC 89, ioapic_edge_54 + IDT_SET_VEC 90, ioapic_edge_55 + IDT_SET_VEC 91, ioapic_edge_56 + IDT_SET_VEC 92, ioapic_edge_57 + IDT_SET_VEC 93, ioapic_edge_58 + IDT_SET_VEC 94, ioapic_edge_59 + IDT_SET_VEC 95, ioapic_edge_60 + IDT_SET_VEC 96, ioapic_edge_61 + IDT_SET_VEC 97, ioapic_edge_62 IDT_SET_VEC 97, ioapic_edge_63 ret |