summaryrefslogtreecommitdiff
path: root/sys
diff options
context:
space:
mode:
Diffstat (limited to 'sys')
-rw-r--r--sys/arch/amd64/amd64/machdep.c12
-rw-r--r--sys/arch/amd64/amd64/tss.c177
-rw-r--r--sys/include/arch/amd64/cpu.h2
-rw-r--r--sys/include/arch/amd64/gdt.h1
-rw-r--r--sys/include/arch/amd64/intr.h4
-rw-r--r--sys/include/arch/amd64/tss.h121
6 files changed, 317 insertions, 0 deletions
diff --git a/sys/arch/amd64/amd64/machdep.c b/sys/arch/amd64/amd64/machdep.c
index 983a480..2fe71a9 100644
--- a/sys/arch/amd64/amd64/machdep.c
+++ b/sys/arch/amd64/amd64/machdep.c
@@ -30,6 +30,7 @@
#include <sys/types.h>
#include <machine/cpu.h>
#include <machine/gdt.h>
+#include <machine/tss.h>
#include <machine/idt.h>
#include <machine/trap.h>
#include <machine/asm.h>
@@ -67,6 +68,16 @@ setup_vectors(void)
idt_set_desc(0xE, IDT_TRAP_GATE, ISR(page_fault), 0);
}
+static inline void
+init_tss(struct cpu_info *ci)
+{
+ struct tss_desc *desc;
+
+ desc = (struct tss_desc *)&g_gdt_data[GDT_TSS];
+ write_tss(ci, desc);
+ tss_load();
+}
+
static void
try_mitigate_spectre(void)
{
@@ -95,6 +106,7 @@ cpu_startup(void)
setup_vectors();
amd64_write_gs_base((uintptr_t)&g_bsp_ci);
+ init_tss(&g_bsp_ci);
try_mitigate_spectre();
lapic_init();
diff --git a/sys/arch/amd64/amd64/tss.c b/sys/arch/amd64/amd64/tss.c
new file mode 100644
index 0000000..5aab74a
--- /dev/null
+++ b/sys/arch/amd64/amd64/tss.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/errno.h>
+#include <sys/panic.h>
+#include <vm/dynalloc.h>
+#include <vm/physmem.h>
+#include <machine/tss.h>
+#include <machine/cpu.h>
+#include <assert.h>
+#include <string.h>
+
+/*
+ * Allocates memory for TSS and kernel
+ * stack.
+ *
+ * XXX: Kernel stack is allocated from
+ * vm_alloc_frame()
+ */
+static void
+alloc_resources(struct cpu_info *ci)
+{
+ const size_t STACK_SIZE = 0x1000;
+ struct tss_entry *tss;
+ static uintptr_t rsp0_base, rsp0;
+
+ if (ci->tss == NULL) {
+ tss = dynalloc(sizeof(*tss));
+
+ if (tss == NULL) {
+ panic("Failed to alloc TSS\n");
+ }
+
+ memset(tss, 0, sizeof(*tss));
+ rsp0_base = vm_alloc_frame(1);
+
+ if (rsp0_base == 0) {
+ panic("Could not allocate RSP0 base\n");
+ }
+
+ rsp0 = rsp0_base + STACK_SIZE;
+ tss->rsp0_lo = rsp0 & 0xFFFFFFFF;
+ tss->rsp0_hi = (rsp0 >> 32) & 0xFFFFFFFF;
+ ci->tss = tss;
+ }
+}
+
+/*
+ * Update interrupt stack table entry `istno' with `stack'
+ *
+ * @stack: Interrupt stack.
+ * @istno: IST number, must be 1-based.
+ *
+ * Returns 0 on success.
+ */
+int
+tss_update_ist(struct cpu_info *ci, union tss_stack stack, uint8_t istno)
+{
+ volatile struct tss_entry *tss = ci->tss;
+
+ __assert(tss != NULL);
+
+ switch (istno) {
+ case 1:
+ tss->ist1_lo = stack.top_lo;
+ tss->ist1_hi = stack.top_hi;
+ break;
+ case 2:
+ tss->ist2_lo = stack.top_lo;
+ tss->ist2_hi = stack.top_hi;
+ break;
+ case 3:
+ tss->ist3_lo = stack.top_lo;
+ tss->ist3_hi = stack.top_hi;
+ break;
+ case 4:
+ tss->ist4_lo = stack.top_lo;
+ tss->ist4_hi = stack.top_hi;
+ break;
+ case 5:
+ tss->ist5_lo = stack.top_lo;
+ tss->ist5_hi = stack.top_hi;
+ break;
+ case 6:
+ tss->ist6_lo = stack.top_lo;
+ tss->ist6_hi = stack.top_hi;
+ break;
+ case 7:
+ tss->ist7_lo = stack.top_lo;
+ tss->ist7_hi = stack.top_hi;
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ return 0;
+}
+
+/*
+ * Allocates TSS stack.
+ *
+ * @entry_out: Pointer to location where allocated entry
+ * will be sent.
+ *
+ * Returns 0 on success.
+ */
+int
+tss_alloc_stack(union tss_stack *entry_out, size_t size)
+{
+ uintptr_t base = (uintptr_t)dynalloc(size);
+
+ if (base == 0) {
+ return -ENOMEM;
+ }
+
+ entry_out->top = base + size;
+ return 0;
+}
+
+void
+write_tss(struct cpu_info *ci, struct tss_desc *desc)
+{
+ volatile struct tss_entry *tss;
+ uintptr_t tss_base;
+
+ alloc_resources(ci);
+ tss_base = (uintptr_t)ci->tss;
+
+ /*
+ * XXX: The AVL (Available for use by system software)
+ * bit is ignored by hardware and it is up to us
+ * to decide how to use it... As of now, it is useless
+ * to us and shall remain 0.
+ */
+ desc->seglimit = sizeof(struct tss_entry);
+ desc->p = 1; /* Must be present to be valid! */
+ desc->g = 0; /* Granularity -> 0 */
+ desc->avl = 0; /* Not used */
+ desc->dpl = 0; /* Descriptor Privilege Level -> 0 */
+ desc->type = 0x9; /* For TSS -> 0x9 (0b1001) */
+
+ desc->base_lo16 = tss_base & 0xFFFF;
+ desc->base_mid8 = (tss_base >> 16) & 0xFF;
+ desc->base_hi_mid8 = (tss_base >> 24) & 0xFF;
+ desc->base_hi32 = (tss_base >> 32) & 0xFFFFFFFF;
+
+ tss = ci->tss;
+ tss->io_base = 0xFF; /* Disallow ring 3 port I/O */
+}
diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h
index 92d2356..ef2eb78 100644
--- a/sys/include/arch/amd64/cpu.h
+++ b/sys/include/arch/amd64/cpu.h
@@ -32,11 +32,13 @@
#include <sys/types.h>
#include <sys/cdefs.h>
+#include <machine/tss.h>
struct cpu_info {
uint32_t apicid;
uint8_t has_x2apic : 1;
size_t lapic_tmr_freq;
+ struct tss_entry *tss;
};
void cpu_startup(void);
diff --git a/sys/include/arch/amd64/gdt.h b/sys/include/arch/amd64/gdt.h
index 6f8a914..ce7dd60 100644
--- a/sys/include/arch/amd64/gdt.h
+++ b/sys/include/arch/amd64/gdt.h
@@ -6,6 +6,7 @@
#define KERNEL_CS 0x08
#define KERNEL_DS 0x10
+#define GDT_TSS 5
struct __packed gdt_entry {
uint16_t limit;
diff --git a/sys/include/arch/amd64/intr.h b/sys/include/arch/amd64/intr.h
index cceab6f..3f0da77 100644
--- a/sys/include/arch/amd64/intr.h
+++ b/sys/include/arch/amd64/intr.h
@@ -32,6 +32,10 @@
#include <sys/types.h>
+#define IST_SCHED 1U
+#define IST_HW_IRQ 2U
+#define IST_SW_INT 3U
+
int intr_alloc_vector(void);
#endif
diff --git a/sys/include/arch/amd64/tss.h b/sys/include/arch/amd64/tss.h
new file mode 100644
index 0000000..347192d
--- /dev/null
+++ b/sys/include/arch/amd64/tss.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MACHINE_TSS_H_
+#define _MACHINE_TSS_H_
+
+#include <sys/types.h>
+#include <sys/cdefs.h>
+
+struct cpu_info;
+
+/*
+ * A TSS entry (64-bit)
+ *
+ * See Intel SDM Section 8.2.1 - Task-State Segment (TSS)
+ */
+struct __packed tss_entry {
+ uint32_t reserved1;
+ uint32_t rsp0_lo;
+ uint32_t rsp0_hi;
+ uint32_t rsp1_lo;
+ uint32_t rsp1_hi;
+ uint32_t rsp2_lo;
+ uint32_t rsp2_hi;
+ uint64_t reserved2;
+ uint32_t ist1_lo;
+ uint32_t ist1_hi;
+ uint32_t ist2_lo;
+ uint32_t ist2_hi;
+ uint32_t ist3_lo;
+ uint32_t ist3_hi;
+ uint32_t ist4_lo;
+ uint32_t ist4_hi;
+ uint32_t ist5_lo;
+ uint32_t ist5_hi;
+ uint32_t ist6_lo;
+ uint32_t ist6_hi;
+ uint32_t ist7_lo;
+ uint32_t ist7_hi;
+ uint64_t reserved3;
+ uint16_t reserved4;
+ uint16_t io_base;
+};
+
+/*
+ * TSS descriptor (64-bit)
+ *
+ * The TSS descriptor describes the location
+ * of the TSS segments among other things...
+ *
+ * See Intel SDM Section 8.2.3 - TSS Descriptor in 64-bit mode
+ */
+struct __packed tss_desc {
+ uint16_t seglimit;
+ uint16_t base_lo16;
+ uint8_t base_mid8;
+ uint8_t type : 4;
+ uint8_t zero : 1;
+ uint8_t dpl : 2;
+ uint8_t p : 1;
+ uint8_t seglimit_hi : 4;
+ uint8_t avl : 1;
+ uint8_t unused : 2;
+ uint8_t g : 1;
+ uint8_t base_hi_mid8;
+ uint32_t base_hi32;
+ uint32_t reserved;
+};
+
+/*
+ * Holds the address of the address pointing
+ * to the top of an interrupt stack.
+ */
+union tss_stack {
+ struct {
+ uint32_t top_lo;
+ uint32_t top_hi;
+ };
+ uint64_t top;
+};
+
+__always_inline static inline void
+tss_load(void)
+{
+ __ASMV("str %ax\n"
+ "mov $0x2B, %ax\n"
+ "ltr %ax"
+ );
+}
+
+int tss_alloc_stack(union tss_stack *entry_out, size_t size);
+int tss_update_ist(struct cpu_info *ci, union tss_stack stack, uint8_t istno);
+void write_tss(struct cpu_info *ci, struct tss_desc *desc);
+
+#endif /* !_MACHINE_TSS_H_ */
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-02 07:33:13 +0000