diff options
Diffstat (limited to 'sys/include')
| -rw-r--r-- | sys/include/arch/amd64/lapic.h | 39 | ||||
| -rw-r--r-- | sys/include/arch/amd64/lapicvar.h | 30 |
2 files changed, 68 insertions, 1 deletions
diff --git a/sys/include/arch/amd64/lapic.h b/sys/include/arch/amd64/lapic.h new file mode 100644 index 0000000..f9d5718 --- /dev/null +++ b/sys/include/arch/amd64/lapic.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2023 Ian Marco Moffett and the VegaOS team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of VegaOS nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AMD64_LAPIC_H_ +#define _AMD64_LAPIC_H_ + +#define LAPIC_TMR_ONESHOT 0x00 +#define LAPIC_TMR_PERIODIC 0x01 + +void lapic_set_base(void *mmio_base); +void lapic_init(void); + +#endif /* !_AMD64_LAPIC_H_ */ diff --git a/sys/include/arch/amd64/lapicvar.h b/sys/include/arch/amd64/lapicvar.h index 262dec0..98b66ef 100644 --- a/sys/include/arch/amd64/lapicvar.h +++ b/sys/include/arch/amd64/lapicvar.h @@ -30,6 +30,8 @@ #ifndef _AMD64_LAPICVAR_H_ #define _AMD64_LAPICVAR_H_ +#include <sys/cdefs.h> + /* LAPIC register offsets */ #define LAPIC_ID 0x0020U /* ID Register */ #define LAPIC_VERSION 0x0030U /* Version Register */ @@ -45,8 +47,34 @@ #define LAPIC_TMR 0x0180U /* Trigger Mode Register (max=0x0220) */ #define LAPIC_IRR 0x0200U /* Interrupt Request Register (max=0x0270) */ #define LAPIC_ERR 0x0280U /* Error Status Register */ +#define LAPIC_LVT_TMR 0x0320U /* LVT Timer Register */ #define LAPIC_DCR 0x03E0U /* Divide Configuration Register (for timer) */ +#define LAPIC_INIT_CNT 0x0380U /* Initial Count Register (for timer) */ +#define LAPIC_CUR_CNT 0x0390U /* Current Count Register (for timer) */ + +#define IA32_APIC_BASE_MSR 0x1B + +/* + * To hardware enable, OR the value + * of the IA32_APIC_BASE MSR with + * LAPIC_HW_ENABLE and rewrite it. + * + * To software enable, OR the value + * of the SVR with LAPIC_SW_ENABLE + * and rewrite it. + * + * LAPIC_SW_ENABLE has the low 8 bits set + * as some hardware requires the spurious + * vector to be hardwired to 1s so we'll + * go with that to be safe. + */ +#define LAPIC_HW_ENABLE __BIT(11) +#define LAPIC_SW_ENABLE (__BIT(8) | 0xFF) + +/* The initial logical APIC ID to be set */ +#define LAPIC_STARTUP_LID 0x1 -#define IA32_APIC_BASE_MSR 0x1B +/* LVT bits */ +#define LAPIC_LVT_MASK __BIT(16) #endif /* !_AMD64_LAPICVAR_H_ */ |