diff options
Diffstat (limited to 'sys/include')
-rw-r--r-- | sys/include/arch/amd64/cpu.h | 6 | ||||
-rw-r--r-- | sys/include/arch/amd64/intr.h | 3 | ||||
-rw-r--r-- | sys/include/crypto/chacha20.h (renamed from sys/include/dev/random/chacha20.h) | 0 | ||||
-rw-r--r-- | sys/include/crypto/siphash.h (renamed from sys/include/dev/random/siphash.h) | 0 | ||||
-rw-r--r-- | sys/include/dev/mii/mii.h | 57 | ||||
-rw-r--r-- | sys/include/dev/phy/et131xregs.h | 275 | ||||
-rw-r--r-- | sys/include/sys/atomic.h | 30 | ||||
-rw-r--r-- | sys/include/sys/limits.h | 2 | ||||
-rw-r--r-- | sys/include/sys/sched.h | 29 | ||||
-rw-r--r-- | sys/include/sys/schedvar.h | 6 |
10 files changed, 404 insertions, 4 deletions
diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h index 46e5df7..a047cef 100644 --- a/sys/include/arch/amd64/cpu.h +++ b/sys/include/arch/amd64/cpu.h @@ -33,6 +33,7 @@ #include <sys/types.h> #include <sys/cdefs.h> #include <sys/proc.h> +#include <sys/sched.h> #include <sys/spinlock.h> #include <machine/tss.h> @@ -45,12 +46,15 @@ struct cpu_info { uint32_t apicid; uint32_t feat; + uint8_t model : 4; /* CPU model number */ + uint8_t family : 4; /* CPU family ID */ uint8_t has_x2apic : 1; uint8_t tlb_shootdown : 1; uint8_t ipl; size_t lapic_tmr_freq; uint8_t irq_mask; vaddr_t shootdown_va; + struct sched_cpu stat; struct tss_entry *tss; struct proc *curtd; struct spinlock lock; @@ -65,6 +69,8 @@ void cpu_enable_smep(void); void cpu_disable_smep(void); struct cpu_info *cpu_get(uint32_t index); +struct sched_cpu *cpu_get_stat(uint32_t cpu_index); + uint32_t cpu_count(void); void cpu_shootdown_tlb(vaddr_t va); diff --git a/sys/include/arch/amd64/intr.h b/sys/include/arch/amd64/intr.h index c848b6f..1877d20 100644 --- a/sys/include/arch/amd64/intr.h +++ b/sys/include/arch/amd64/intr.h @@ -69,9 +69,11 @@ struct intr_data { * [r]: Required for intr_register() * [o]: Not required for intr_register() * [v]: Returned by intr_register() + * [i]: Internal * * @func: The actual handler [r] * @data: Interrupt data [o/v] + * @nintr: Number of times it fired [o] * @name: Interrupt name [v] * @priority: Interrupt priority [r] * @irq: Interrupt request number [o] @@ -91,6 +93,7 @@ struct intr_data { */ struct intr_hand { int(*func)(void *); + size_t nintr; struct intr_data data; char *name; int priority; diff --git a/sys/include/dev/random/chacha20.h b/sys/include/crypto/chacha20.h index d35702a..d35702a 100644 --- a/sys/include/dev/random/chacha20.h +++ b/sys/include/crypto/chacha20.h diff --git a/sys/include/dev/random/siphash.h b/sys/include/crypto/siphash.h index ecabb4a..ecabb4a 100644 --- a/sys/include/dev/random/siphash.h +++ b/sys/include/crypto/siphash.h diff --git a/sys/include/dev/mii/mii.h b/sys/include/dev/mii/mii.h new file mode 100644 index 0000000..5d77281 --- /dev/null +++ b/sys/include/dev/mii/mii.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_MII_H_ +#define _DEV_MII_H_ + +#include <sys/param.h> + +/* + * MII registers + */ +#define MII_BMCR 0x00 /* Basic Mode Config */ +#define MII_BMSR 0x01 /* Basic Mode Status */ +#define MII_PHYID 0x02 /* MII PHY identifier 1 */ +#define MII_PHYID2 0x03 /* MII PHY identifier 2 */ +#define MII_ADVER 0x04 /* Auto-negotiation advertisement */ +#define MII_LPA 0x05 /* Link parter abilities */ +#define MII_EXPAN 0x06 /* Auto-negotiation expansion */ +#define MII_ESTATUS 0x0F /* Extended status register */ +#define MII_IRQ 0x1B /* Interrupt control/status */ + +/* + * MII BMCR bits + */ +#define MII_BMCR_RST BIT(15) /* PHY reset */ +#define MII_BCMR_LOOP BIT(14) /* Loopback mode enable */ +#define MII_BMCR_ANEN BIT(12) /* Auto-negotiation enable */ +#define MII_PWR_DOWN BIT(11) /* Power down PHY */ +#define MII_ISOLATE BIT(10) /* Electrically isolate PHY from MII */ + +#endif /* !_DEV_MII_H_ */ diff --git a/sys/include/dev/phy/et131xregs.h b/sys/include/dev/phy/et131xregs.h new file mode 100644 index 0000000..1f8bfcb --- /dev/null +++ b/sys/include/dev/phy/et131xregs.h @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Please refer to share/docs/hw/et131x.txt + */ + +#ifndef _PHYS_ET131XREGS_H_ +#define _PHYS_ET131XREGS_H_ + +#include <sys/types.h> + +#define MAC_CFG1_SOFTRST 0x80000000 /* Soft reset */ +#define MAC_CFG1_SIMRST 0x40000000 /* SIM reset */ +#define MAC_CFG1_RESET_RXMC 0x00080000 /* RX MC reset */ +#define MAC_CFG1_RESET_TXMC 0x00040000 /* TX MC reset */ +#define MAC_CFG1_RESET_RXFUNC 0x00020000 /* RX func reset */ +#define MAC_CFG1_RESET_TXFUNC 0x00010000 /* TX func reset */ + +#define PAD_N(N, NAME) uint8_t (NAME)[(N)] + +/* + * ET131X global registers + */ +struct global_regs { + uint32_t txq_start; + uint32_t txq_end; + uint32_t rxq_start; + uint32_t rxq_end; + uint32_t pm_csr; + uint32_t unused; + uint32_t istat; + uint32_t imask; + uint32_t ialias_clr_en; + uint32_t istat_alias; + uint32_t sw_reset; + uint32_t slv_timer; + uint32_t msi_config; + uint32_t loopback; + uint32_t watchdog_timer; +}; + +/* + * ET131X TX DMA registers + */ +struct txdma_regs { + uint32_t csr; + uint32_t pr_base_hi; + uint32_t pr_base_lo; + uint32_t pr_num_des; + uint32_t txq_wr_addr; + uint32_t txq_wr_addr_ext; + uint32_t txq_rd_addr; + uint32_t dma_wb_base_hi; + uint32_t dma_wb_base_lo; + uint32_t service_request; + uint32_t service_complete; + uint32_t cache_rd_index; + uint32_t cache_wr_index; + uint32_t tx_dma_error; + uint32_t des_abort_cnt; + uint32_t payload_abort_cnt; + uint32_t wb_abort_cnt; + uint32_t des_timeout_cnt; + uint32_t payload_timeout_cnt; + uint32_t wb_timeout_cnt; + uint32_t des_error_cnt; + uint32_t payload_err_cnt; + uint32_t wb_error_cnt; + uint32_t dropped_tlp_cnt; + uint32_t new_service_complete; + uint32_t ether_pkt_cnt; +}; + +/* + * ET131X RX DMA registers + */ +struct rxdma_regs { + uint32_t csr; + uint32_t dma_wb_base_lo; + uint32_t dma_wb_base_hi; + uint32_t num_pkt_done; + uint32_t max_pkt_time; + uint32_t rxq_rd_addr; + uint32_t rxq_rd_addr_ext; + uint32_t rxq_wr_addr; + uint32_t psr_base_lo; + uint32_t psr_base_hi; + uint32_t psr_num_des; + uint32_t psr_avail_offset; + uint32_t psr_full_offset; + uint32_t psr_access_index; + uint32_t psr_min_des; + uint32_t fbr0_base_lo; + uint32_t fbr0_base_hi; + uint32_t fbr0_num_des; + uint32_t fbr0_avail_offset; + uint32_t fbr0_full_offset; + uint32_t fbr0_rd_index; + uint32_t fbr0_min_des; + uint32_t fbr1_base_lo; + uint32_t fbr1_base_hi; + uint32_t fbr1_num_des; + uint32_t fbr1_avail_offset; + uint32_t fbr1_full_offset; + uint32_t fbr1_rd_index; + uint32_t fbr1_min_des; +}; + +/* + * ET131X TX MAC registers + */ +struct txmac_regs { + uint32_t ctl; + uint32_t shadow_ptr; + uint32_t err_cnt; + uint32_t max_fill; + uint32_t cf_param; + uint32_t tx_test; + uint32_t err; + uint32_t err_int; + uint32_t bp_ctrl; +}; + +/* + * ET131X RX MAC registers + */ +struct rxmac_regs { + uint32_t ctrl; + uint32_t crc0; + uint32_t crc12; + uint32_t crc34; + uint32_t sa_lo; + uint32_t sa_hi; + uint32_t mask0_word0; + uint32_t mask0_word1; + uint32_t mask0_word2; + uint32_t mask0_word3; + uint32_t mask1_word0; + uint32_t mask1_word1; + uint32_t mask1_word2; + uint32_t mask1_word3; + uint32_t mask2_word0; + uint32_t mask2_word1; + uint32_t mask2_word2; + uint32_t mask2_word3; + uint32_t mask3_word0; + uint32_t mask3_word1; + uint32_t mask3_word2; + uint32_t mask3_word3; + uint32_t mask4_word0; + uint32_t mask4_word1; + uint32_t mask4_word2; + uint32_t mask4_word3; + uint32_t uni_pf_addr1; + uint32_t uni_pf_addr2; + uint32_t uni_pf_addr3; + uint32_t multi_hash1; + uint32_t multi_hash2; + uint32_t multi_hash3; + uint32_t multi_hash4; + uint32_t pf_ctrl; + uint32_t mcif_ctrl_max_seg; + uint32_t mcif_water_mark; + uint32_t rxq_diag; + uint32_t space_avail; + uint32_t mif_ctrl; + uint32_t err_reg; +}; + +struct mac_regs { + uint32_t cfg1; + uint32_t cfg2; + uint32_t ipg; + uint32_t hfdp; + uint32_t max_fm_len; + uint32_t rsv1; + uint32_t rsv2; + uint32_t mac_test; + uint32_t mii_mgmt_cfg; + uint32_t mii_mgmt_cmd; + uint32_t mii_mgmt_addr; + uint32_t mii_mgmt_ctrl; + uint32_t mii_mgmt_stat; + uint32_t mii_mgmt_indicator; + uint32_t if_ctrl; + uint32_t if_stat; + uint32_t station_addr_1; + uint32_t station_addr_2; +}; + +/* Global reset */ +#define GBL_RESET_ALL 0x007F + +/* MII management address */ +#define MAC_MII_ADDR(PHY, REG) ((PHY) << 8 | (REG)) + +/* MAC management indications */ +#define MAC_MGMT_BUSY 0x00000001 +#define MAC_MGMT_WAIT 0x00000005 + +/* MAC management config values */ +#define MAC_MIIMGMT_CLK_RST 0x00007 + +/* LED register defines */ +#define PHY_LED2 0x1C + +/* PCI config space offsets */ +#define PCI_EEPROM_STATUS 0xB2 +#define PCI_MAC_ADDRESS 0xA4 + +/* + * LED control register 2 values + */ +#define LED_BLINK 0xD +#define LED_ON 0xE +#define LED_OFF 0xF +#define LED_ALL_OFF 0xFFFF + +/* + * LED register bit-shift constants + * + * Bits [3:0]: 100BASE-T LED + * Bits [7:4]: 100BASE-TX LED + * Bits [11:8]: TX/RX LED + * Bits [15:12]: Link LED + */ +#define LED_TXRX_SHIFT 8 +#define LED_LINK_SHIFT 12 + +struct et131x_iospace { +#define _IO_PAD(NAME, REGSET) uint8_t NAME[4096 - sizeof(struct REGSET)] + struct global_regs global; + _IO_PAD(global_pad, global_regs); + struct txdma_regs txdma; + _IO_PAD(txdma_pad, txdma_regs); + struct rxdma_regs rxdma; + _IO_PAD(rxdma_pad, rxdma_regs); + struct txmac_regs txmac; + _IO_PAD(txmac_pad, txmac_regs); + struct rxmac_regs rxmac; + _IO_PAD(rxmac_pad, rxmac_regs); + struct mac_regs mac; + _IO_PAD(mac_pad, mac_regs); + /* ... TODO - add more */ +#undef _IO_PAD +}; + +#endif /* !_PHYS_ET131XREGS_H_ */ diff --git a/sys/include/sys/atomic.h b/sys/include/sys/atomic.h index f61bf62..d9b3bde 100644 --- a/sys/include/sys/atomic.h +++ b/sys/include/sys/atomic.h @@ -30,6 +30,8 @@ #ifndef _SYS_ATOMIC_H_ #define _SYS_ATOMIC_H_ +#include <sys/types.h> + static inline unsigned long atomic_add_long_nv(volatile unsigned long *p, unsigned long v) { @@ -42,6 +44,12 @@ atomic_add_int_nv(volatile unsigned int *p, unsigned int v) return __sync_add_and_fetch(p, v); } +static inline unsigned int +atomic_add_64_nv(volatile uint64_t *p, unsigned int v) +{ + return __sync_add_and_fetch(p, v); +} + static inline unsigned long atomic_sub_long_nv(volatile unsigned long *p, unsigned long v) { @@ -55,6 +63,12 @@ atomic_sub_int_nv(volatile unsigned int *p, unsigned int v) } static inline unsigned int +atomic_sub_64_nv(volatile uint64_t *p, unsigned int v) +{ + return __sync_sub_and_fetch(p, v); +} + +static inline unsigned int atomic_load_int_nv(volatile unsigned int *p, unsigned int v) { return __atomic_load_n(p, v); @@ -66,6 +80,12 @@ atomic_load_long_nv(volatile unsigned long *p, unsigned int v) return __atomic_load_n(p, v); } +static inline unsigned int +atomic_load_64_nv(volatile uint64_t *p, unsigned int v) +{ + return __atomic_load_n(p, v); +} + static inline void atomic_store_int_nv(volatile unsigned int *p, int nv, unsigned int v) { @@ -78,20 +98,30 @@ atomic_store_long_nv(volatile unsigned long *p, long nv, unsigned int v) __atomic_store_n(p, nv, v); } +static inline void +atomic_store_64_nv(volatile uint64_t *p, long nv, unsigned int v) +{ + __atomic_store_n(p, nv, v); +} + /* Atomic increment (and fetch) operations */ #define atomic_inc_long(P) atomic_add_long_nv((P), 1) #define atomic_inc_int(P) atomic_add_int_nv((P), 1) +#define atomic_inc_64(P) atomic_add_64_nv((P), 1) /* Atomic decrement (and fetch) operations */ #define atomic_dec_long(P) atomic_sub_long_nv((P), 1) #define atomic_dec_int(P) atomic_sub_int_nv((P), 1) +#define atomic_dec_64(P) atomic_sub_64_nv((P), 1) /* Atomic load operations */ #define atomic_load_int(P) atomic_load_int_nv((P), __ATOMIC_SEQ_CST) #define atomic_load_long(P) atomic_load_long_nv((P), __ATOMIC_SEQ_CST) +#define atomic_load_64(P) atomic_load_64_nv((P), __ATOMIC_SEQ_CST) /* Atomic store operations */ #define atomic_store_int(P, NV) atomic_store_int_nv((P), (NV), __ATOMIC_SEQ_CST) #define atomic_store_long(P, NV) atomic_store_long_nv((P), (NV), __ATOMIC_SEQ_CST) +#define atomic_store_64(P, NV) atomic_store_64_nv((P), (NV), __ATOMIC_SEQ_CST) #endif /* !_SYS_ATOMIC_H_ */ diff --git a/sys/include/sys/limits.h b/sys/include/sys/limits.h index 5b97b68..f6aed9d 100644 --- a/sys/include/sys/limits.h +++ b/sys/include/sys/limits.h @@ -35,7 +35,5 @@ #define SSIZE_MAX 32767 #define ARG_MAX 4096 #define CHAR_BIT 8 -#if defined(_KERNEL) #define CPU_MAX 256 -#endif /* _KERNEL */ #endif /* !_SYS_LIMITS_H_ */ diff --git a/sys/include/sys/sched.h b/sys/include/sys/sched.h index 7d17607..abc2718 100644 --- a/sys/include/sys/sched.h +++ b/sys/include/sys/sched.h @@ -32,13 +32,38 @@ #include <sys/proc.h> #include <sys/cdefs.h> +#include <sys/limits.h> + +/* + * Scheduler CPU information + * + * @nswitch: Number of context switches + * @idle: Number of milliseconds idle + */ +struct sched_cpu { + uint32_t nswitch; +}; + +/* + * Scheduler statistics + * + * @nproc: Number processes running + * @ncpu: Number of CPU cores + * @quantum_usec: Scheduler quantum (microseconds) + */ +struct sched_stat { + size_t nproc; + uint16_t ncpu; + uint32_t quantum_usec; + struct sched_cpu cpus[CPU_MAX]; +}; #if defined(_KERNEL) +void sched_stat(struct sched_stat *statp); void sched_init(void); -void sched_yield(void); -void sched_switch_to(struct trapframe *tf, struct proc *td); +void sched_yield(void); void sched_detach(struct proc *td); __dead void sched_enter(void); diff --git a/sys/include/sys/schedvar.h b/sys/include/sys/schedvar.h index 5ed9f5f..017fcb7 100644 --- a/sys/include/sys/schedvar.h +++ b/sys/include/sys/schedvar.h @@ -60,5 +60,11 @@ struct sched_queue { size_t nthread; }; +struct proc *sched_dequeue_td(void); +void mi_sched_switch(struct proc *from); + +void md_sched_switch(struct trapframe *tf); +void sched_oneshot(bool now); + #endif /* _KERNEL */ #endif /* !_SYS_SCHEDVAR_H_ */ |