diff options
Diffstat (limited to 'sys/include/dev')
| -rw-r--r-- | sys/include/dev/acpi/tables.h | 98 | ||||
| -rw-r--r-- | sys/include/dev/acpi/uacpi/uacpi/internal/namespace.h | 1 | ||||
| -rw-r--r-- | sys/include/dev/acpi/uacpi/uacpi/platform/config.h | 1 | ||||
| -rw-r--r-- | sys/include/dev/acpi/uacpi/uacpi/utilities.h | 1 | ||||
| -rw-r--r-- | sys/include/dev/cons/ansi.h | 75 | ||||
| -rw-r--r-- | sys/include/dev/cons/cons.h | 21 | ||||
| -rw-r--r-- | sys/include/dev/dmi/dmi.h | 42 | ||||
| -rw-r--r-- | sys/include/dev/dmi/dmivar.h | 41 | ||||
| -rw-r--r-- | sys/include/dev/ic/ahciregs.h | 7 | ||||
| -rw-r--r-- | sys/include/dev/ic/ahcivar.h | 2 | ||||
| -rw-r--r-- | sys/include/dev/ic/nvmevar.h | 85 | ||||
| -rw-r--r-- | sys/include/dev/mii/mii.h | 57 | ||||
| -rw-r--r-- | sys/include/dev/pci/pci.h | 1 | ||||
| -rw-r--r-- | sys/include/dev/phy/e1000regs.h | 119 | ||||
| -rw-r--r-- | sys/include/dev/phy/et131xregs.h | 275 | ||||
| -rw-r--r-- | sys/include/dev/phy/rtl.h (renamed from sys/include/dev/phy/rt8139.h) | 3 | ||||
| -rw-r--r-- | sys/include/dev/random/entropy.h | 40 | ||||
| -rw-r--r-- | sys/include/dev/timer.h | 6 | ||||
| -rw-r--r-- | sys/include/dev/usb/xhciregs.h | 1 | ||||
| -rw-r--r-- | sys/include/dev/video/fbdev.h | 1 |
20 files changed, 871 insertions, 6 deletions
diff --git a/sys/include/dev/acpi/tables.h b/sys/include/dev/acpi/tables.h index 5215c86..d31cbe0 100644 --- a/sys/include/dev/acpi/tables.h +++ b/sys/include/dev/acpi/tables.h @@ -118,6 +118,43 @@ struct __packed acpi_gas { uint64_t address; }; +/* + * ACPI Address Space ID definitions for GAS + * + * See section 5.2.3.2 of the ACPI software programming + * manual. + * + * XXX: 0x0B->0x7E is reserved as well as 0x80->0xBF + * and 0xC0->0xFF is OEM defined. Values other than + * the ones specified below are either garbage or + * OEM specific values. + */ +#define ACPI_GAS_SYSMEM 0x00 /* System memory space */ +#define ACPI_GAS_SYSIO 0x01 /* System I/O space */ +#define ACPI_GAS_PCICONF 0x02 /* PCI configuration space */ +#define ACPI_GAS_EC 0x03 /* Embedded controller */ +#define ACPI_GAS_SMBUS 0x04 /* System management bus */ +#define ACPI_GAS_CMOS 0x05 /* System CMOS */ +#define ACPI_GAS_PCIBAR 0x06 /* PCI BAR target */ +#define ACPI_GAS_IPMI 0x07 /* IPMI (sensor monitoring) */ +#define ACPI_GAS_GPIO 0x08 /* General Purpose I/O */ +#define ACPI_GAS_GSBUS 0x09 /* GenericSerialBus */ +#define ACPI_GAS_PLATCOM 0x0A /* Platform Communications Channel */ + +/* + * ACPI address size definitions for GAS + * + * See section 5.2.3.2 of the ACPI software programming + * manual. + * + * This is really retarded Intel and Microsoft, thank you. + */ +#define ACPI_GAS_UNDEF 0 /* Undefined (legacy reasons) */ +#define ACPI_GAS_BYTE 1 /* Byte access */ +#define ACPI_GAS_WORD 2 /* Word access */ +#define ACPI_GAS_DWORD 3 /* Dword access */ +#define ACPI_GAS_QWORD 4 /* Qword access */ + struct __packed acpi_hpet { struct acpi_header hdr; uint8_t hardware_rev_id; @@ -132,4 +169,65 @@ struct __packed acpi_hpet { uint8_t page_protection; }; +/* + * PCIe / ACPI MCFG base address description + * table. + * + * @base_pa: Enhanced configuration base [physical] + * @seg_grpno: PCI segment group number + * @bus_start: Host bridge bus start + * @bus_end: Host bridge bus end + */ +struct __packed acpi_mcfg_base { + uint64_t base_pa; + uint16_t seg_grpno; + uint8_t bus_start; + uint8_t bus_end; + uint32_t reserved; +}; + +/* + * PCIe / ACPI MCFG structure + * + * @hdr: ACPI header + * @reserved: Do not use + * @base: ECAM MMIO address list + */ +struct __packed acpi_mcfg { + struct acpi_header hdr; + uint32_t reserved[2]; + struct acpi_mcfg_base base[1]; +}; + +struct __packed dmi_entry32 { + char signature[4]; /* _SM_ */ + uint8_t checksum; /* Sum of table bytes */ + uint8_t length; /* Length of entry table */ + uint8_t major; /* DMI major */ + uint8_t minor; /* DMI minor */ + uint16_t max_size; /* Max structure size */ + uint8_t rev; /* Entry revision */ + char fmt_area[5]; /* Formatted area */ + char isignature[5]; /* Intermediate signature */ + uint8_t ichecksum; /* Intermediate checksum */ + uint16_t table_len; /* Length of SMBIOS structure table */ + uint32_t addr; /* 32-bit physical start of SMBIOS structure table */ + uint16_t nstruct; /* Total number of structures */ + uint8_t bcd_rev; +}; + +struct __packed dmi_entry64 { + char signature[5]; /* _SM_ */ + uint8_t checksum; /* Sum of table bytes */ + uint8_t length; /* Length of entry table */ + uint8_t major; /* DMI major */ + uint8_t minor; /* DMI minor */ + uint8_t docrev; + uint8_t entry_rev; + uint8_t reserved; + uint16_t max_size; /* Max structure size */ + uint16_t padding; + uint64_t addr; /* 64-bit physical address */ +}; + #endif /* _ACPI_TABLES_H_ */ diff --git a/sys/include/dev/acpi/uacpi/uacpi/internal/namespace.h b/sys/include/dev/acpi/uacpi/uacpi/internal/namespace.h index 369c5a4..045e402 100644 --- a/sys/include/dev/acpi/uacpi/uacpi/internal/namespace.h +++ b/sys/include/dev/acpi/uacpi/uacpi/internal/namespace.h @@ -42,7 +42,6 @@ void uacpi_deinitialize_namespace(void); uacpi_namespace_node *uacpi_namespace_node_alloc(uacpi_object_name name); void uacpi_namespace_node_unref(uacpi_namespace_node *node); - uacpi_status uacpi_namespace_node_type_unlocked( const uacpi_namespace_node *node, uacpi_object_type *out_type ); diff --git a/sys/include/dev/acpi/uacpi/uacpi/platform/config.h b/sys/include/dev/acpi/uacpi/uacpi/platform/config.h index dff043f..b594338 100644 --- a/sys/include/dev/acpi/uacpi/uacpi/platform/config.h +++ b/sys/include/dev/acpi/uacpi/uacpi/platform/config.h @@ -67,7 +67,6 @@ UACPI_BUILD_BUG_ON_WITH_MSG( */ // #define UACPI_SIZED_FREES - /* * Makes uacpi_kernel_alloc_zeroed mandatory to implement by the host, uACPI * will not provide a default implementation if this is enabled. diff --git a/sys/include/dev/acpi/uacpi/uacpi/utilities.h b/sys/include/dev/acpi/uacpi/uacpi/utilities.h index dfc41c3..d7042e9 100644 --- a/sys/include/dev/acpi/uacpi/uacpi/utilities.h +++ b/sys/include/dev/acpi/uacpi/uacpi/utilities.h @@ -128,7 +128,6 @@ uacpi_status uacpi_eval_cls(uacpi_namespace_node*, uacpi_id_string **out_id); */ uacpi_status uacpi_eval_uid(uacpi_namespace_node*, uacpi_id_string **out_uid); - // uacpi_namespace_node_info->flags #define UACPI_NS_NODE_INFO_HAS_ADR (1 << 0) #define UACPI_NS_NODE_INFO_HAS_HID (1 << 1) diff --git a/sys/include/dev/cons/ansi.h b/sys/include/dev/cons/ansi.h new file mode 100644 index 0000000..7a336d1 --- /dev/null +++ b/sys/include/dev/cons/ansi.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CONS_ANSI_H_ +#define _CONS_ANSI_H_ + +#include <sys/types.h> +#include <sys/cdefs.h> +#include <sys/param.h> + +/* ANSI colors */ +#define ANSI_BLACK 0x000000 +#define ANSI_RED 0xAA0000 +#define ANSI_GREEN 0x00AA00 +#define ANSI_BLUE 0x00007F +#define ANSI_YELLOW 0xAA5500 +#define ANSI_MAGENTA 0xAA00AA +#define ANSI_CYAN 0x00AAAA +#define ANSI_WHITE 0xAAAAAA + +/* ANSI_FEED update codes */ +#define ANSI_UPDATE_COLOR -1 +#define ANSI_UPDATE_CURSOR -2 + +/* + * ANSI parser state machine. + * + * @prev: Previous char + * @csi: Encountered control seq introducer + * @reset_color: 1 if color is to be reset + * @set_fg: 1 if fg is being set + * @set_bg: 1 if bg is being set + * @fg: Foreground color + * @bg: Background color + * @flags: State flags + */ +struct ansi_state { + char prev; + uint8_t csi : 2; + uint8_t reset_color : 1; + uint8_t set_fg : 1; + uint8_t set_bg : 1; + uint32_t fg; + uint32_t bg; +}; + +int ansi_feed(struct ansi_state *statep, char c); + +#endif /* !_CONS_ANSI_H_ */ diff --git a/sys/include/dev/cons/cons.h b/sys/include/dev/cons/cons.h index 3569c52..7c4e41a 100644 --- a/sys/include/dev/cons/cons.h +++ b/sys/include/dev/cons/cons.h @@ -32,8 +32,12 @@ #include <sys/types.h> #include <sys/spinlock.h> +#include <sys/proc.h> +#include <sys/mutex.h> +#include <sys/console.h> #include <dev/video/fbdev.h> #include <dev/cons/consvar.h> +#include <dev/cons/ansi.h> struct cons_char { char c; @@ -45,6 +49,11 @@ struct cons_char { struct cons_screen { struct fbdev fbdev; + struct ansi_state ansi_s; + struct console_feat feat; /* Features */ + struct console_attr attr; /* Attributes */ + struct proc *atproc; /* Attached proc */ + struct mutex *atproc_lock; uint32_t fg; uint32_t bg; @@ -54,17 +63,25 @@ struct cons_screen { uint32_t ncols; uint32_t ch_col; /* Current col */ uint32_t ch_row; /* Current row */ - uint32_t curs_col; /* Cursor col */ - uint32_t curs_row; /* Cursor row */ struct cons_buf *ib; /* Input buffer */ struct cons_buf **ob; /* Output buffers */ struct cons_char last_chr; struct spinlock lock; }; +#define curs_col attr.cursor_x +#define curs_row attr.cursor_y + void cons_init(void); void cons_expose(void); +void cons_update_color(struct cons_screen *scr, uint32_t fg, uint32_t bg); +void cons_clear_scr(struct cons_screen *scr, uint32_t bg); +void cons_reset_color(struct cons_screen *scr); +void cons_reset_cursor(struct cons_screen *scr); +int cons_attach(void); +int cons_detach(void); int cons_putch(struct cons_screen *scr, char c); +int cons_putstr(struct cons_screen *scr, const char *s, size_t len); extern struct cons_screen g_root_scr; diff --git a/sys/include/dev/dmi/dmi.h b/sys/include/dev/dmi/dmi.h new file mode 100644 index 0000000..8b7030c --- /dev/null +++ b/sys/include/dev/dmi/dmi.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DMI_DMI_H_ +#define _DMI_DMI_H_ + +#include <sys/types.h> + +const char *dmi_vendor(void); +const char *dmi_prodver(void); +const char *dmi_prodfam(void); +const char *dmi_product(void); +const char *dmi_cpu_manufact(void); +const char *dmi_cpu_version(void); + +#endif /* !_DMI_DMI_H_ */ diff --git a/sys/include/dev/dmi/dmivar.h b/sys/include/dev/dmi/dmivar.h new file mode 100644 index 0000000..e5da92f --- /dev/null +++ b/sys/include/dev/dmi/dmivar.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_DMIVAR_H_ +#define _DEV_DMIVAR_H_ + +#include <sys/types.h> +#include <sys/sio.h> +#include <fs/ctlfs.h> + +extern struct ctlops g_ctl_board_ident; + +int dmi_board_ctl_read(struct ctlfs_dev *cdp, struct sio_txn *sio); + +#endif /* !_DEV_DMIVAR_H_ */ diff --git a/sys/include/dev/ic/ahciregs.h b/sys/include/dev/ic/ahciregs.h index f959a1e..232b41e 100644 --- a/sys/include/dev/ic/ahciregs.h +++ b/sys/include/dev/ic/ahciregs.h @@ -88,6 +88,7 @@ struct hba_memspace { */ #define AHCI_PXSSTS_DET(SSTS) (SSTS & 0xF) #define AHCI_PXSSTS_IPM(SSTS) ((SSTS >> 8) & 0xF) +#define AHCI_PXSSTS_SPD(SSTS) ((SSTS >> 4) & 0xF) /* * Port SATA control bits @@ -100,6 +101,7 @@ struct hba_memspace { * See section 3.3.7 of the AHCI spec. */ #define AHCI_PXCMD_ST BIT(0) /* Start */ +#define AHCI_PXCMD_SUD BIT(1) /* Spin-up device */ #define AHCI_PXCMD_FRE BIT(4) /* FIS Receive Enable */ #define AHCI_PXCMD_FR BIT(14) /* FIS Receive Running */ #define AHCI_PXCMD_CR BIT(15) /* Command List Running */ @@ -137,6 +139,9 @@ struct hba_memspace { #define AHCI_DET_PRESENT 1 /* Device present (no PHY comm) */ #define AHCI_DET_COMM 3 /* Device present and phy comm established */ #define AHCI_IPM_ACTIVE 1 +#define AHCI_SPD_GEN1 1 /* 1.5 Gb/s */ +#define AHCI_SPD_GEN2 2 /* 3 Gb/s */ +#define AHCI_SPD_GEN3 3 /* 6 Gb/s */ /* * PxSERR bits @@ -158,6 +163,8 @@ struct hba_memspace { #define AHCI_DIAG_T BIT(24) /* Transport state transition error */ #define AHCI_DIAG_F BIT(25) /* Unknown FIS type */ +#define ATAPI_SIG 0xEB140101 + /* * Device detection initialization values * See section 3.3.11 of the AHCI spec. diff --git a/sys/include/dev/ic/ahcivar.h b/sys/include/dev/ic/ahcivar.h index a23a654..67f2efe 100644 --- a/sys/include/dev/ic/ahcivar.h +++ b/sys/include/dev/ic/ahcivar.h @@ -96,6 +96,7 @@ struct ahci_hba { * @io: Memory mapped port registers * @hba: HBA descriptor * @cmdlist: Command list [p] + * @nlba: Max number of addressable blocks * @fra: FIS receive area [p] * @dev: Device minor number. */ @@ -104,6 +105,7 @@ struct hba_device { struct ahci_hba *hba; struct ahci_cmd_hdr *cmdlist; struct dcdr *dcdr; + uint32_t nlba; void *fra; dev_t dev; }; diff --git a/sys/include/dev/ic/nvmevar.h b/sys/include/dev/ic/nvmevar.h index eab8b52..f361d0a 100644 --- a/sys/include/dev/ic/nvmevar.h +++ b/sys/include/dev/ic/nvmevar.h @@ -31,9 +31,11 @@ #define _IC_NVMEVAR_H_ #include <sys/types.h> +#include <sys/cdefs.h> /* Admin commands */ #define NVME_OP_CREATE_IOSQ 0x01 +#define NVME_OP_GET_LOGPAGE 0x02 #define NVME_OP_CREATE_IOCQ 0x05 #define NVME_OP_IDENTIFY 0x06 @@ -45,6 +47,67 @@ #define NVME_OP_WRITE 0x01 #define NVME_OP_READ 0x02 +/* Log page identifiers */ +#define NVME_LOGPAGE_SMART 0x02 + +/* + * S.M.A.R.T health / information log + * + * See section 5.16.1.3, figure 207 of the + * NVMe base spec (rev 2.0a) + * + * @cwarn: Critical warning + * @temp: Composite tempature (kelvin) + * @avail_spare: Available spare (in percentage) + * @avail_spare_thr: Available spare threshold + * @percent_used: Estimate NVMe life used percentage + * @end_cwarn: Endurance group critical warning summary + * @data_units_read: Number of 512 byte data units read + * @data_units_written: Number of 512 byte data units written + * @host_reads: Number of host read commands completed + * @host_writes: Number of host write commands completed + * @ctrl_busy_time: Controller busy time + * @power_cycles: Number of power cycles + * @power_on_hours: Number of power on hours + * @unsafe_shutdowns: Number of unsafe shutdowns + * @media_errors: Media and data integrity errors + * @n_errlog_entries: Number of error log info entries + * @warning_temp_time: Warning composite tempature time + * @critical_comp_time: Critical composite tempature time + * @temp_sensor: Tempature sensor <n> data + * @temp1_trans_cnt: Tempature 1 transition count + * @temp2_trans_cnt: Tempature 2 transition count + * @temp1_total_time: Total time for tempature 1 + * @temp2_total_time: Total time for tempature 2 + */ +struct __packed nvme_smart_data { + uint8_t cwarn; + uint16_t temp; + uint8_t avail_spare; + uint8_t avail_spare_thr; + uint8_t percent_used; + uint8_t end_cwarn; + uint8_t reserved[25]; + uint8_t data_units_read[16]; + uint8_t data_units_written[16]; + uint8_t host_reads[16]; + uint8_t host_writes[16]; + uint8_t ctrl_busy_time[16]; + uint8_t power_cycles[16]; + uint8_t power_on_hours[16]; + uint8_t unsafe_shutdowns[16]; + uint8_t media_errors[16]; + uint8_t n_errlog_entries[16]; + uint32_t warning_temp_time; + uint32_t critical_comp_time; + uint16_t temp_sensor[8]; + uint32_t temp1_trans_cnt; + uint32_t temp2_trans_cnt; + uint32_t temp1_total_time; + uint32_t temp2_total_time; + uint8_t reserved1[280]; +}; + struct nvme_identify_cmd { uint8_t opcode; uint8_t flags; @@ -98,6 +161,26 @@ struct nvme_create_iosq_cmd { uint64_t unused3[2]; }; +/* Get log page */ +struct nvme_get_logpage_cmd { + uint8_t opcode; + uint8_t flags; + uint16_t cid; + uint32_t nsid; + uint64_t unused[2]; + uint64_t prp1; + uint64_t prp2; + uint8_t lid; + uint8_t lsp; + uint16_t numdl; + uint16_t numdu; + uint16_t lsi; + uint64_t lpo; + uint8_t unused1[3]; + uint8_t csi; + uint32_t unused2; +}; + /* Read/write */ struct nvme_rw_cmd { uint8_t opcode; @@ -117,12 +200,12 @@ struct nvme_rw_cmd { uint16_t appmask; }; - struct nvme_cmd { union { struct nvme_identify_cmd identify; struct nvme_create_iocq_cmd create_iocq; struct nvme_create_iosq_cmd create_iosq; + struct nvme_get_logpage_cmd get_logpage; struct nvme_rw_cmd rw; }; }; diff --git a/sys/include/dev/mii/mii.h b/sys/include/dev/mii/mii.h new file mode 100644 index 0000000..5d77281 --- /dev/null +++ b/sys/include/dev/mii/mii.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_MII_H_ +#define _DEV_MII_H_ + +#include <sys/param.h> + +/* + * MII registers + */ +#define MII_BMCR 0x00 /* Basic Mode Config */ +#define MII_BMSR 0x01 /* Basic Mode Status */ +#define MII_PHYID 0x02 /* MII PHY identifier 1 */ +#define MII_PHYID2 0x03 /* MII PHY identifier 2 */ +#define MII_ADVER 0x04 /* Auto-negotiation advertisement */ +#define MII_LPA 0x05 /* Link parter abilities */ +#define MII_EXPAN 0x06 /* Auto-negotiation expansion */ +#define MII_ESTATUS 0x0F /* Extended status register */ +#define MII_IRQ 0x1B /* Interrupt control/status */ + +/* + * MII BMCR bits + */ +#define MII_BMCR_RST BIT(15) /* PHY reset */ +#define MII_BCMR_LOOP BIT(14) /* Loopback mode enable */ +#define MII_BMCR_ANEN BIT(12) /* Auto-negotiation enable */ +#define MII_PWR_DOWN BIT(11) /* Power down PHY */ +#define MII_ISOLATE BIT(10) /* Electrically isolate PHY from MII */ + +#endif /* !_DEV_MII_H_ */ diff --git a/sys/include/dev/pci/pci.h b/sys/include/dev/pci/pci.h index a4de162..144b500 100644 --- a/sys/include/dev/pci/pci.h +++ b/sys/include/dev/pci/pci.h @@ -62,6 +62,7 @@ struct pci_device { uint8_t pci_subclass; uint8_t prog_if; uint8_t hdr_type; + uint8_t pci_express : 1; uint8_t pri_bus; uint8_t sec_bus; diff --git a/sys/include/dev/phy/e1000regs.h b/sys/include/dev/phy/e1000regs.h new file mode 100644 index 0000000..7caceee --- /dev/null +++ b/sys/include/dev/phy/e1000regs.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PHY_E1000_REGS_H_ +#define _PHY_E1000_REGS_H_ + +#include <sys/types.h> +#include <sys/param.h> + +/* + * E1000 register offsets + * + * XXX: Notes about reserve fields: + * + * - The `EERD' register is reserved and should NOT be touched + * for the 82544GC/EI card. + * + * - The `FLA' register is only usable for the 82541xx and + * 82547GI/EI cards, this is reserved and should NOT be + * touched on any other cards. + * + * - The `TXCW' and `RXCW' registers are reserved and should NOT + * be touched for the 82540EP/EM, 82541xx and 82547GI/EI cards. + * + * - The `LEDCTL' register is reserved and should NOT be touched + * for the 82544GC/EI card. + */ +#define E1000_CTL 0x00000 /* Control register */ +#define E1000_STATUS 0x00008 /* Status register */ +#define E1000_EECD 0x00010 /* EEPROM/flash control and data register */ +#define E1000_EERD 0x00014 /* EEPROM/flash read register */ +#define E1000_FLA 0x0001C /* EEPROM/flash read register */ +#define E1000_CTRL_EXT 0x00018 /* Extended device control register */ +#define E1000_MDIC 0x00020 /* PHY management data interface control register */ +#define E1000_FCAL 0x00028 /* Flow control low register */ +#define E1000_FCAH 0x0002C /* Flow control high register */ +#define E1000_FCT 0x00030 /* Flow control type register */ +#define E1000_VET 0x00038 /* VLAN ethertype register */ +#define E1000_FCTTV 0x00170 /* Flow control transmit timer value register */ +#define E1000_TXCW 0x00178 /* Transmit config word register */ +#define E1000_RXCW 0x00180 /* Receive config word register */ +#define E1000_LEDCTL 0x00E00 /* LED control register */ + +/* + * Device control register (`ctl') bits + * + * See section 13.4.1 of the PCI/PCI-X Intel Gigabit + * Ethernet Controllers spec + * + * XXX: Notes about reserved bits: + * + * - The CTL.LRST bit is reserved and should NOT be touched + * for the 82540EP/EM, 82541xx, or 82547GI/EI cards. + */ +#define E1000_CTL_FD BIT(0) /* Full-duplex */ +#define E1000_CTL_LRST BIT(3) /* Link-reset */ +#define E1000_CTL_RST BIT(26) /* Device reset */ + +/* + * EEPROM/flash control and data register (`eecd') + * bits + * + * See section 13.4.3 of the PCI/PCI-X Intel Gigabit + * Ethernet controller spec + */ +#define E1000_EECD_SK BIT(0) /* EEPROM clock input */ +#define E1000_EECD_CS BIT(1) /* EEPROM chip select */ +#define E1000_EECD_DI BIT(2) /* EEPROM data input */ +#define E1000_EECD_DO BIT(3) /* EEPROM data output */ +#define E1000_EECD_FWE BIT(4) /* EEPROM flash write enable ctl (4:5) */ +#define E1000_EECD_REQ BIT(6) /* Request EEPROM access */ +#define E1000_EECD_GNT BIT(7) /* Grant EEPROM access */ +#define E1000_EECD_PRES BIT(8) /* EEPROM present */ +#define E1000_EECD_SIZE BIT(9) /* EEPROM size (1024-bit [0], 4096-bit [1]) */ +#define E1000_EECD_TYPE BIT(13) /* EEPROM type (microwire [0], SPI [1]) */ + +/* + * EEPROM read (`eerd') register bits + * + * See section 13.4.4 of the PCI/PCI-X Intel Gigabit + * Ethernet controller spec + */ +#define E1000_EERD_START BIT(0) /* Start read */ +#define E1000_EERD_DONE BIT(4) /* EEPROM read finished */ + +/* + * EEPROM word addresses + */ +#define E1000_HWADDR0 0x00 /* Word 0 */ +#define E1000_HWADDR1 0x01 /* Word 1 */ +#define E1000_HWADDR2 0x02 /* Word 2 */ + +#endif /* !_PHY_E1000_REGS_H_ */ diff --git a/sys/include/dev/phy/et131xregs.h b/sys/include/dev/phy/et131xregs.h new file mode 100644 index 0000000..1f8bfcb --- /dev/null +++ b/sys/include/dev/phy/et131xregs.h @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Please refer to share/docs/hw/et131x.txt + */ + +#ifndef _PHYS_ET131XREGS_H_ +#define _PHYS_ET131XREGS_H_ + +#include <sys/types.h> + +#define MAC_CFG1_SOFTRST 0x80000000 /* Soft reset */ +#define MAC_CFG1_SIMRST 0x40000000 /* SIM reset */ +#define MAC_CFG1_RESET_RXMC 0x00080000 /* RX MC reset */ +#define MAC_CFG1_RESET_TXMC 0x00040000 /* TX MC reset */ +#define MAC_CFG1_RESET_RXFUNC 0x00020000 /* RX func reset */ +#define MAC_CFG1_RESET_TXFUNC 0x00010000 /* TX func reset */ + +#define PAD_N(N, NAME) uint8_t (NAME)[(N)] + +/* + * ET131X global registers + */ +struct global_regs { + uint32_t txq_start; + uint32_t txq_end; + uint32_t rxq_start; + uint32_t rxq_end; + uint32_t pm_csr; + uint32_t unused; + uint32_t istat; + uint32_t imask; + uint32_t ialias_clr_en; + uint32_t istat_alias; + uint32_t sw_reset; + uint32_t slv_timer; + uint32_t msi_config; + uint32_t loopback; + uint32_t watchdog_timer; +}; + +/* + * ET131X TX DMA registers + */ +struct txdma_regs { + uint32_t csr; + uint32_t pr_base_hi; + uint32_t pr_base_lo; + uint32_t pr_num_des; + uint32_t txq_wr_addr; + uint32_t txq_wr_addr_ext; + uint32_t txq_rd_addr; + uint32_t dma_wb_base_hi; + uint32_t dma_wb_base_lo; + uint32_t service_request; + uint32_t service_complete; + uint32_t cache_rd_index; + uint32_t cache_wr_index; + uint32_t tx_dma_error; + uint32_t des_abort_cnt; + uint32_t payload_abort_cnt; + uint32_t wb_abort_cnt; + uint32_t des_timeout_cnt; + uint32_t payload_timeout_cnt; + uint32_t wb_timeout_cnt; + uint32_t des_error_cnt; + uint32_t payload_err_cnt; + uint32_t wb_error_cnt; + uint32_t dropped_tlp_cnt; + uint32_t new_service_complete; + uint32_t ether_pkt_cnt; +}; + +/* + * ET131X RX DMA registers + */ +struct rxdma_regs { + uint32_t csr; + uint32_t dma_wb_base_lo; + uint32_t dma_wb_base_hi; + uint32_t num_pkt_done; + uint32_t max_pkt_time; + uint32_t rxq_rd_addr; + uint32_t rxq_rd_addr_ext; + uint32_t rxq_wr_addr; + uint32_t psr_base_lo; + uint32_t psr_base_hi; + uint32_t psr_num_des; + uint32_t psr_avail_offset; + uint32_t psr_full_offset; + uint32_t psr_access_index; + uint32_t psr_min_des; + uint32_t fbr0_base_lo; + uint32_t fbr0_base_hi; + uint32_t fbr0_num_des; + uint32_t fbr0_avail_offset; + uint32_t fbr0_full_offset; + uint32_t fbr0_rd_index; + uint32_t fbr0_min_des; + uint32_t fbr1_base_lo; + uint32_t fbr1_base_hi; + uint32_t fbr1_num_des; + uint32_t fbr1_avail_offset; + uint32_t fbr1_full_offset; + uint32_t fbr1_rd_index; + uint32_t fbr1_min_des; +}; + +/* + * ET131X TX MAC registers + */ +struct txmac_regs { + uint32_t ctl; + uint32_t shadow_ptr; + uint32_t err_cnt; + uint32_t max_fill; + uint32_t cf_param; + uint32_t tx_test; + uint32_t err; + uint32_t err_int; + uint32_t bp_ctrl; +}; + +/* + * ET131X RX MAC registers + */ +struct rxmac_regs { + uint32_t ctrl; + uint32_t crc0; + uint32_t crc12; + uint32_t crc34; + uint32_t sa_lo; + uint32_t sa_hi; + uint32_t mask0_word0; + uint32_t mask0_word1; + uint32_t mask0_word2; + uint32_t mask0_word3; + uint32_t mask1_word0; + uint32_t mask1_word1; + uint32_t mask1_word2; + uint32_t mask1_word3; + uint32_t mask2_word0; + uint32_t mask2_word1; + uint32_t mask2_word2; + uint32_t mask2_word3; + uint32_t mask3_word0; + uint32_t mask3_word1; + uint32_t mask3_word2; + uint32_t mask3_word3; + uint32_t mask4_word0; + uint32_t mask4_word1; + uint32_t mask4_word2; + uint32_t mask4_word3; + uint32_t uni_pf_addr1; + uint32_t uni_pf_addr2; + uint32_t uni_pf_addr3; + uint32_t multi_hash1; + uint32_t multi_hash2; + uint32_t multi_hash3; + uint32_t multi_hash4; + uint32_t pf_ctrl; + uint32_t mcif_ctrl_max_seg; + uint32_t mcif_water_mark; + uint32_t rxq_diag; + uint32_t space_avail; + uint32_t mif_ctrl; + uint32_t err_reg; +}; + +struct mac_regs { + uint32_t cfg1; + uint32_t cfg2; + uint32_t ipg; + uint32_t hfdp; + uint32_t max_fm_len; + uint32_t rsv1; + uint32_t rsv2; + uint32_t mac_test; + uint32_t mii_mgmt_cfg; + uint32_t mii_mgmt_cmd; + uint32_t mii_mgmt_addr; + uint32_t mii_mgmt_ctrl; + uint32_t mii_mgmt_stat; + uint32_t mii_mgmt_indicator; + uint32_t if_ctrl; + uint32_t if_stat; + uint32_t station_addr_1; + uint32_t station_addr_2; +}; + +/* Global reset */ +#define GBL_RESET_ALL 0x007F + +/* MII management address */ +#define MAC_MII_ADDR(PHY, REG) ((PHY) << 8 | (REG)) + +/* MAC management indications */ +#define MAC_MGMT_BUSY 0x00000001 +#define MAC_MGMT_WAIT 0x00000005 + +/* MAC management config values */ +#define MAC_MIIMGMT_CLK_RST 0x00007 + +/* LED register defines */ +#define PHY_LED2 0x1C + +/* PCI config space offsets */ +#define PCI_EEPROM_STATUS 0xB2 +#define PCI_MAC_ADDRESS 0xA4 + +/* + * LED control register 2 values + */ +#define LED_BLINK 0xD +#define LED_ON 0xE +#define LED_OFF 0xF +#define LED_ALL_OFF 0xFFFF + +/* + * LED register bit-shift constants + * + * Bits [3:0]: 100BASE-T LED + * Bits [7:4]: 100BASE-TX LED + * Bits [11:8]: TX/RX LED + * Bits [15:12]: Link LED + */ +#define LED_TXRX_SHIFT 8 +#define LED_LINK_SHIFT 12 + +struct et131x_iospace { +#define _IO_PAD(NAME, REGSET) uint8_t NAME[4096 - sizeof(struct REGSET)] + struct global_regs global; + _IO_PAD(global_pad, global_regs); + struct txdma_regs txdma; + _IO_PAD(txdma_pad, txdma_regs); + struct rxdma_regs rxdma; + _IO_PAD(rxdma_pad, rxdma_regs); + struct txmac_regs txmac; + _IO_PAD(txmac_pad, txmac_regs); + struct rxmac_regs rxmac; + _IO_PAD(rxmac_pad, rxmac_regs); + struct mac_regs mac; + _IO_PAD(mac_pad, mac_regs); + /* ... TODO - add more */ +#undef _IO_PAD +}; + +#endif /* !_PHYS_ET131XREGS_H_ */ diff --git a/sys/include/dev/phy/rt8139.h b/sys/include/dev/phy/rtl.h index 21c7d54..f3178d0 100644 --- a/sys/include/dev/phy/rt8139.h +++ b/sys/include/dev/phy/rtl.h @@ -71,6 +71,9 @@ #define RT_AS_LPAR 0x68 /* Auto-negotiation link partner reg (16 bits) */ #define RT_AS_EXPANSION 0x6A /* Auto-negotiation expansion reg (16 bits) */ +#define RT_TXAD_N(N) (RT_TXADDR0 + (N)) +#define RT_TXSTATUS_N(N) (RT_TXSTATUS0 + ((N))) + /* Command register bits */ #define RT_BUFEN BIT(0) /* Buffer empty */ #define RT_TE BIT(2) /* Transmitter enable */ diff --git a/sys/include/dev/random/entropy.h b/sys/include/dev/random/entropy.h new file mode 100644 index 0000000..34d86df --- /dev/null +++ b/sys/include/dev/random/entropy.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <stdint.h> + +#define ENTROPY_POOL_SIZE 32 + +struct entropy_pool { + uint8_t pool[ENTROPY_POOL_SIZE]; + uint32_t entropy_bits; +}; + +void mix_entropy(struct entropy_pool *ep, const uint8_t *input, + size_t input_len, uint32_t input_entropy_bits); diff --git a/sys/include/dev/timer.h b/sys/include/dev/timer.h index e54adcc..2ca6d62 100644 --- a/sys/include/dev/timer.h +++ b/sys/include/dev/timer.h @@ -31,11 +31,15 @@ #define _DEV_TIMER_H_ #include <sys/types.h> +#include <sys/param.h> /* Timer IDs */ #define TIMER_SCHED 0x00000000U /* Scheduler reserved timer */ #define TIMER_GP 0x00000001U /* General purpose timer */ +/* Timer flags */ +#define TIMER_MONOTONIC BIT(0) + /* Number of timer IDs, adjust when adding timer IDs */ #define TIMER_ID_COUNT 2 @@ -69,6 +73,7 @@ struct timer { const char *name; /* e.g "HPET" */ size_t(*calibrate)(void); /* Returns frequency, 0 for unspecified */ size_t(*get_time_usec)(void); /* Time since init (microseconds) */ + size_t(*get_time_nsec)(void); /* Time since init (nanoseconds) */ size_t(*get_time_sec)(void); /* Time since init (seconds) */ int(*msleep)(size_t ms); int(*usleep)(size_t us); @@ -78,6 +83,7 @@ struct timer { void(*oneshot_ms)(size_t ms); void(*oneshot_us)(size_t ms); void(*stop)(void); + uint8_t flags; }; tmrr_status_t register_timer(timer_id_t id, const struct timer *tmr); diff --git a/sys/include/dev/usb/xhciregs.h b/sys/include/dev/usb/xhciregs.h index 1cbfd14..cafd7c9 100644 --- a/sys/include/dev/usb/xhciregs.h +++ b/sys/include/dev/usb/xhciregs.h @@ -77,6 +77,7 @@ struct xhci_opregs { /* USBSTS bits */ #define USBSTS_HCH BIT(0) /* HC halted */ +#define USBSTS_CNR BIT(11) /* Controller not ready */ /* CAPS.HCSPARAMS1 fields */ #define XHCI_MAXSLOTS(HCSPARAMS1) (HCSPARAMS1 & 0xFF) diff --git a/sys/include/dev/video/fbdev.h b/sys/include/dev/video/fbdev.h index c80fd92..c9fec94 100644 --- a/sys/include/dev/video/fbdev.h +++ b/sys/include/dev/video/fbdev.h @@ -52,5 +52,6 @@ fbdev_get_index(const struct fbdev *fbdev, uint32_t x, uint32_t y) } struct fbdev fbdev_get(void); +void fbdev_init_dev(void); #endif /* !_DEV_FBDEV_H_ */ |