diff options
Diffstat (limited to 'sys/include/dev/phy')
| -rw-r--r-- | sys/include/dev/phy/e1000regs.h | 119 | ||||
| -rw-r--r-- | sys/include/dev/phy/rtl.h | 105 |
2 files changed, 224 insertions, 0 deletions
diff --git a/sys/include/dev/phy/e1000regs.h b/sys/include/dev/phy/e1000regs.h new file mode 100644 index 0000000..7caceee --- /dev/null +++ b/sys/include/dev/phy/e1000regs.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PHY_E1000_REGS_H_ +#define _PHY_E1000_REGS_H_ + +#include <sys/types.h> +#include <sys/param.h> + +/* + * E1000 register offsets + * + * XXX: Notes about reserve fields: + * + * - The `EERD' register is reserved and should NOT be touched + * for the 82544GC/EI card. + * + * - The `FLA' register is only usable for the 82541xx and + * 82547GI/EI cards, this is reserved and should NOT be + * touched on any other cards. + * + * - The `TXCW' and `RXCW' registers are reserved and should NOT + * be touched for the 82540EP/EM, 82541xx and 82547GI/EI cards. + * + * - The `LEDCTL' register is reserved and should NOT be touched + * for the 82544GC/EI card. + */ +#define E1000_CTL 0x00000 /* Control register */ +#define E1000_STATUS 0x00008 /* Status register */ +#define E1000_EECD 0x00010 /* EEPROM/flash control and data register */ +#define E1000_EERD 0x00014 /* EEPROM/flash read register */ +#define E1000_FLA 0x0001C /* EEPROM/flash read register */ +#define E1000_CTRL_EXT 0x00018 /* Extended device control register */ +#define E1000_MDIC 0x00020 /* PHY management data interface control register */ +#define E1000_FCAL 0x00028 /* Flow control low register */ +#define E1000_FCAH 0x0002C /* Flow control high register */ +#define E1000_FCT 0x00030 /* Flow control type register */ +#define E1000_VET 0x00038 /* VLAN ethertype register */ +#define E1000_FCTTV 0x00170 /* Flow control transmit timer value register */ +#define E1000_TXCW 0x00178 /* Transmit config word register */ +#define E1000_RXCW 0x00180 /* Receive config word register */ +#define E1000_LEDCTL 0x00E00 /* LED control register */ + +/* + * Device control register (`ctl') bits + * + * See section 13.4.1 of the PCI/PCI-X Intel Gigabit + * Ethernet Controllers spec + * + * XXX: Notes about reserved bits: + * + * - The CTL.LRST bit is reserved and should NOT be touched + * for the 82540EP/EM, 82541xx, or 82547GI/EI cards. + */ +#define E1000_CTL_FD BIT(0) /* Full-duplex */ +#define E1000_CTL_LRST BIT(3) /* Link-reset */ +#define E1000_CTL_RST BIT(26) /* Device reset */ + +/* + * EEPROM/flash control and data register (`eecd') + * bits + * + * See section 13.4.3 of the PCI/PCI-X Intel Gigabit + * Ethernet controller spec + */ +#define E1000_EECD_SK BIT(0) /* EEPROM clock input */ +#define E1000_EECD_CS BIT(1) /* EEPROM chip select */ +#define E1000_EECD_DI BIT(2) /* EEPROM data input */ +#define E1000_EECD_DO BIT(3) /* EEPROM data output */ +#define E1000_EECD_FWE BIT(4) /* EEPROM flash write enable ctl (4:5) */ +#define E1000_EECD_REQ BIT(6) /* Request EEPROM access */ +#define E1000_EECD_GNT BIT(7) /* Grant EEPROM access */ +#define E1000_EECD_PRES BIT(8) /* EEPROM present */ +#define E1000_EECD_SIZE BIT(9) /* EEPROM size (1024-bit [0], 4096-bit [1]) */ +#define E1000_EECD_TYPE BIT(13) /* EEPROM type (microwire [0], SPI [1]) */ + +/* + * EEPROM read (`eerd') register bits + * + * See section 13.4.4 of the PCI/PCI-X Intel Gigabit + * Ethernet controller spec + */ +#define E1000_EERD_START BIT(0) /* Start read */ +#define E1000_EERD_DONE BIT(4) /* EEPROM read finished */ + +/* + * EEPROM word addresses + */ +#define E1000_HWADDR0 0x00 /* Word 0 */ +#define E1000_HWADDR1 0x01 /* Word 1 */ +#define E1000_HWADDR2 0x02 /* Word 2 */ + +#endif /* !_PHY_E1000_REGS_H_ */ diff --git a/sys/include/dev/phy/rtl.h b/sys/include/dev/phy/rtl.h new file mode 100644 index 0000000..f3178d0 --- /dev/null +++ b/sys/include/dev/phy/rtl.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PHY_RT8139_H_ +#define _PHY_RT8139_H_ + +#include <sys/types.h> +#include <sys/param.h> + +/* MAC address */ +#define RT_IDR0 0x00 +#define RT_IDR1 0x00 +#define RT_IDR2 0x02 +#define RT_IDR3 0x03 +#define RT_IDR4 0x04 +#define RT_IDR5 0x05 + +#define RT_MAR0 0x08 /* Multicast filter */ +#define RT_TXSTATUS0 0x10 /* Transmit status (4 32bit regs) */ +#define RT_TXADDR0 0x20 /* Tx descriptors (also 4 32bit) */ +#define RT_RXBUF 0x30 /* Receive buffer start address */ +#define RT_RXEARLYCNT 0x34 /* Early Rx byte count */ +#define RT_RXEARLYSTATUS 0x36 /* Early Rx status */ +#define RT_CHIPCMD 0x37 /* Command register */ +#define RT_RXBUFTAIL 0x38 /* Current address of packet read (queue tail) */ +#define RT_RXBUFHEAD 0x3A /* Current buffer address (queue head) */ +#define RT_INTRMASK 0x3C /* Interrupt mask */ +#define RT_INTRSTATUS 0x3E /* Interrupt status */ +#define RT_TXCONFIG 0x40 /* Tx config */ +#define RT_RXCONFIG 0x44 /* Rx config */ +#define RT_TIMER 0x48 /* A general purpose counter */ +#define RT_RXMISSED 0x4C /* 24 bits valid, write clears */ +#define RT_CFG9346 0x50 /* 93C46 command register */ +#define RT_CONFIG0 0x51 /* Configuration reg 0 */ +#define RT_CONFIG1 0x52 /* Configuration reg 1 */ +#define RT_TIMERINT 0x54 /* Timer interrupt register (32 bits) */ +#define RT_MEDIASTATUS 0x58 /* Media status register */ +#define RT_CONFIG3 0x59 /* Config register 3 */ +#define RT_CONFIG4 0x5A /* Config register 4 */ +#define RT_MULTIINTR 0x5C /* Multiple interrupt select */ +#define RT_MII_TSAD 0x60 /* Transmit status of all descriptors (16 bits) */ +#define RT_MII_BMCR 0x62 /* Basic Mode Control Register (16 bits) */ +#define RT_MII_BMSR 0x64 /* Basic Mode Status Register (16 bits) */ +#define RT_AS_ADVERT 0x66 /* Auto-negotiation advertisement reg (16 bits) */ +#define RT_AS_LPAR 0x68 /* Auto-negotiation link partner reg (16 bits) */ +#define RT_AS_EXPANSION 0x6A /* Auto-negotiation expansion reg (16 bits) */ + +#define RT_TXAD_N(N) (RT_TXADDR0 + (N)) +#define RT_TXSTATUS_N(N) (RT_TXSTATUS0 + ((N))) + +/* Command register bits */ +#define RT_BUFEN BIT(0) /* Buffer empty */ +#define RT_TE BIT(2) /* Transmitter enable */ +#define RT_RE BIT(3) /* Receiver enable */ +#define RT_RST BIT(4) /* Reset */ + +/* 93C46 EEPROM mode bits */ +#define RT_EEM0 BIT(6) +#define RT_EEM1 BIT(7) + +/* Receive register bits */ +#define RT_AAP BIT(0) /* Accept all packets */ +#define RT_APM BIT(1) /* Accept physical match packets */ +#define RT_AM BIT(2) /* Accept multicast packets */ +#define RT_AB BIT(3) /* Accept brodcast packets */ +#define RT_AR BIT(4) /* Accept runt */ +#define RT_AER BIT(5) /* Accept error packet */ +#define RT_WRAP BIT(6) /* RX wrap */ + +/* Interrupt mask bits */ +#define RT_ROK BIT(0) /* Receive OK */ +#define RT_RER BIT(1) /* Receive error */ +#define RT_TOK BIT(2) /* Transmit OK */ +#define RT_ACKW 0x0005 /* RX/TX ACK word */ + +/* Register poll timeout */ +#define RT_TIMEOUT_MSEC 500 + +#endif /* !_PHY_RT8139_H_ */ |