summaryrefslogtreecommitdiff
path: root/sys/include/dev/ic
diff options
context:
space:
mode:
Diffstat (limited to 'sys/include/dev/ic')
-rw-r--r--sys/include/dev/ic/ahciregs.h36
-rw-r--r--sys/include/dev/ic/ahcivar.h198
2 files changed, 232 insertions, 2 deletions
diff --git a/sys/include/dev/ic/ahciregs.h b/sys/include/dev/ic/ahciregs.h
index 4a4dc65..232b41e 100644
--- a/sys/include/dev/ic/ahciregs.h
+++ b/sys/include/dev/ic/ahciregs.h
@@ -34,8 +34,10 @@
#include <sys/param.h>
struct hba_port {
- volatile uint64_t clb; /* Command list base (1k-byte aligned) */
- volatile uint64_t fb; /* FIS base (256-byte aligned) */
+ volatile uint32_t clb; /* Command list base low (1k-byte aligned) */
+ volatile uint32_t clbu; /* Command list base upper */
+ volatile uint32_t fb; /* FIS base (256-byte aligned) */
+ volatile uint32_t fbu; /* FIS base upper */
volatile uint32_t is; /* Interrupt status */
volatile uint32_t ie; /* Interrupt enable */
volatile uint32_t cmd; /* Command and status */
@@ -86,6 +88,7 @@ struct hba_memspace {
*/
#define AHCI_PXSSTS_DET(SSTS) (SSTS & 0xF)
#define AHCI_PXSSTS_IPM(SSTS) ((SSTS >> 8) & 0xF)
+#define AHCI_PXSSTS_SPD(SSTS) ((SSTS >> 4) & 0xF)
/*
* Port SATA control bits
@@ -98,6 +101,7 @@ struct hba_memspace {
* See section 3.3.7 of the AHCI spec.
*/
#define AHCI_PXCMD_ST BIT(0) /* Start */
+#define AHCI_PXCMD_SUD BIT(1) /* Spin-up device */
#define AHCI_PXCMD_FRE BIT(4) /* FIS Receive Enable */
#define AHCI_PXCMD_FR BIT(14) /* FIS Receive Running */
#define AHCI_PXCMD_CR BIT(15) /* Command List Running */
@@ -122,6 +126,9 @@ struct hba_memspace {
*/
#define AHCI_CAP_NP(CAP) (CAP & 0x1F) /* Number of ports */
#define AHCI_CAP_NCS(CAP) ((CAP >> 8) & 0x1F) /* Number of command slots */
+#define AHCI_CAP_EMS(CAP) ((CAP >> 6) & 1) /* Enclosure management support */
+#define AHCI_CAP_SAL(CAP) ((CAP >> 25) & 1) /* Supports activity LED */
+#define AHCI_CAP_SSS(CAP) ((CAP >> 27) & 1) /* Supports staggered spin up */
/*
* Device detection (DET) and Interface power
@@ -132,6 +139,31 @@ struct hba_memspace {
#define AHCI_DET_PRESENT 1 /* Device present (no PHY comm) */
#define AHCI_DET_COMM 3 /* Device present and phy comm established */
#define AHCI_IPM_ACTIVE 1
+#define AHCI_SPD_GEN1 1 /* 1.5 Gb/s */
+#define AHCI_SPD_GEN2 2 /* 3 Gb/s */
+#define AHCI_SPD_GEN3 3 /* 6 Gb/s */
+
+/*
+ * PxSERR bits
+ * See section 3.3.12 of the AHCI spec
+ */
+#define AHCI_SERR_I BIT(0) /* Recovered data integrity error */
+#define AHCI_SERR_M BIT(1) /* Recovered comms error */
+#define AHCI_SERR_T BIT(8) /* Transient data integrity error */
+#define AHCI_SERR_C BIT(9) /* Persistent comms error */
+#define AHCI_SERR_P BIT(10) /* Protocol error ("oh fuck!" bit) */
+#define AHCI_SERR_E BIT(11) /* Internal error (only God knows, just pray) */
+#define AHCI_DIAG_N BIT(16) /* PhyRdy change */
+#define AHCI_DIAG_I BIT(17) /* PHY internal error */
+#define AHCI_DIAG_W BIT(18) /* Comm wake */
+#define AHCI_DIAG_B BIT(19) /* 10B to 8B decode error */
+#define AHCI_DIAG_C BIT(21) /* CRC error */
+#define AHCI_DIAG_H BIT(22) /* Handshake error */
+#define AHCI_DIAG_S BIT(23) /* Link sequence error */
+#define AHCI_DIAG_T BIT(24) /* Transport state transition error */
+#define AHCI_DIAG_F BIT(25) /* Unknown FIS type */
+
+#define ATAPI_SIG 0xEB140101
/*
* Device detection initialization values
diff --git a/sys/include/dev/ic/ahcivar.h b/sys/include/dev/ic/ahcivar.h
index 0d307cd..67f2efe 100644
--- a/sys/include/dev/ic/ahcivar.h
+++ b/sys/include/dev/ic/ahcivar.h
@@ -30,12 +30,210 @@
#ifndef _IC_AHCIVAR_H_
#define _IC_AHCIVAR_H_
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/device.h>
+#include <dev/dcdr/cache.h>
#include <dev/ic/ahciregs.h>
+#include <fs/ctlfs.h>
+#define AHCI_DCDR_CAP 16
+
+struct ahci_cmd_hdr;
+extern const struct ctlops g_sata_bsize_ops;
+
+struct ata_identity {
+ uint16_t rsvd0 : 1;
+ uint16_t unused0 : 1;
+ uint16_t incomplete : 1;
+ uint16_t unused1 : 3;
+ uint16_t fixed_dev : 1;
+ uint16_t removable : 1;
+ uint16_t unused2 : 7;
+ uint16_t device_type : 1;
+ uint16_t ncylinders;
+ uint16_t specific_config;
+ uint16_t nheads;
+ uint16_t unused3[2];
+ uint16_t sectors_per_track;
+ uint16_t vendor[3];
+ char serial_number[20];
+ uint16_t unused4[2];
+ uint16_t unused5;
+ char firmware_rev[8];
+ char model_number[40];
+ char pad[256];
+};
+
+/*
+ * AHCI Host Bus Adapter
+ *
+ * @io: HBA MMIO
+ * @maxports: Max number of HBA ports
+ * @nports: Number of implemented HBA ports.
+ * @nslots: Number of command slots
+ * @ems: Enclosure management support
+ * @sal: Supports activity LED
+ * @sss: Supports staggered spin up
+ */
struct ahci_hba {
struct hba_memspace *io;
+ uint32_t maxports;
+ uint32_t nports;
+ uint32_t nslots;
+ uint8_t ems : 1;
+ uint8_t sal : 1;
+ uint8_t sss : 1;
+ devmajor_t major;
+};
+
+/*
+ * A device attached to a physical HBA port.
+ *
+ * [d]: Dynalloc'd memory
+ * [p]: Paged memory (allocated pageframe)
+ *
+ * @io: Memory mapped port registers
+ * @hba: HBA descriptor
+ * @cmdlist: Command list [p]
+ * @nlba: Max number of addressable blocks
+ * @fra: FIS receive area [p]
+ * @dev: Device minor number.
+ */
+struct hba_device {
+ struct hba_port *io;
+ struct ahci_hba *hba;
+ struct ahci_cmd_hdr *cmdlist;
+ struct dcdr *dcdr;
+ uint32_t nlba;
+ void *fra;
+ dev_t dev;
+};
+
+/*
+ * Command header
+ *
+ * @cfl: Command FIS length
+ * @a: ATAPI
+ * @w: Write
+ * @p: Prefetchable
+ * @r: Reset
+ * @c: Clear busy upon R_OK
+ * @rsvd0: Reserved
+ * @pmp: Port multiplier port
+ * @prdtl: PRDT length (in entries)
+ * @prdbc: PRDT bytes transferred count
+ * @ctba: Command table descriptor base addr
+ * @rsvd1: Reserved
+ */
+struct ahci_cmd_hdr {
+ uint8_t cfl : 5;
+ uint8_t a : 1;
+ uint8_t w : 1;
+ uint8_t p : 1;
+ uint8_t r : 1;
+ uint8_t c : 1;
+ uint8_t rsvd0 : 1;
+ uint8_t pmp : 4;
+ uint16_t prdtl;
+ volatile uint32_t prdbc;
+ uintptr_t ctba;
+ uint32_t rsvd1[4];
+};
+
+/*
+ * Physical region descriptor
+ *
+ * @dba: Data base address
+ * @rsvd0: Reserved
+ * @dbc: Count
+ * @rsvd1: Reserved
+ * @i: Interrupt on completion
+ */
+struct ahci_prdt_entry {
+ uintptr_t dba;
+ uint32_t rsvd0;
+ uint32_t dbc : 22;
+ uint16_t rsvd1 : 9;
+ uint8_t i : 1;
+};
+
+/*
+ * Command table
+ *
+ * @cfis: Command FIS
+ * @acmd: ATAPI command
+ * @rsvd: Reserved
+ * @prdt: Physical region descriptors
+ */
+struct ahci_cmdtab {
+ uint8_t cfis[64];
+ uint8_t acmd[16];
+ uint8_t rsvd[48];
+ struct ahci_prdt_entry prdt[1];
+};
+
+/*
+ * Host to device FIS
+ *
+ * [h]: Set by host
+ * [d]: Set by device
+ * [srb]: Shadow register block
+ *
+ * @type: Must be 0x27 for H2D [h]
+ * @pmp: Port multiplier port [h]
+ * @c: Set to denote command FIS [h]
+ * @command: Command type [h/srb]
+ * @feature1: Features register (7:0) [h/srb]
+ * @lba0: LBA low [h/srb]
+ * @lba1: LBA mid [h/srb]
+ * @lba2: LBA hi [h/srb]
+ * @device: Set bit 7 for LBA [h/srb]
+ * @lba3: LBA (31:24) [h/srb]
+ * @lba4: LBA (39:32) [h/srb]
+ * @lba5: LBA (47:40) [h/srb]
+ * @featureh: Features high [h/srb]
+ * @countl: Count low (block aligned) [h/srb]
+ * @counth: Count high (block aligned) [h/srb]
+ */
+struct ahci_fis_h2d {
+ uint8_t type;
+ uint8_t pmp : 4;
+ uint8_t rsvd0 : 3;
+ uint8_t c : 1;
+ uint8_t command;
+ uint8_t featurel;
+ uint8_t lba0;
+ uint8_t lba1;
+ uint8_t lba2;
+ uint8_t device;
+ uint8_t lba3;
+ uint8_t lba4;
+ uint8_t lba5;
+ uint8_t featureh;
+ uint8_t countl;
+ uint8_t counth;
+ uint8_t icc;
+ uint8_t control;
+ uint8_t rsvd1[4];
};
#define AHCI_TIMEOUT 500 /* In ms */
+/* AHCI size constants */
+#define AHCI_FIS_SIZE 256
+#define AHCI_CMDTAB_SIZE 256
+#define AHCI_CMDENTRY_SIZE 32
+#define AHCI_SECTOR_SIZE 512
+
+/* AHCI FIS types */
+#define FIS_TYPE_H2D 0x27
+#define FIS_TYPE_D2H 0x34
+
+/* ATA commands */
+#define ATA_CMD_NOP 0x00
+#define ATA_CMD_IDENTIFY 0xEC
+#define ATA_CMD_READ_DMA 0x25
+#define ATA_CMD_WRITE_DMA 0x35
+
#endif /* !_IC_AHCIVAR_H_ */
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-01 03:34:53 +0000