diff options
Diffstat (limited to 'sys/include/dev/ic/ahciregs.h')
| -rw-r--r-- | sys/include/dev/ic/ahciregs.h | 36 |
1 files changed, 34 insertions, 2 deletions
diff --git a/sys/include/dev/ic/ahciregs.h b/sys/include/dev/ic/ahciregs.h index 4a4dc65..232b41e 100644 --- a/sys/include/dev/ic/ahciregs.h +++ b/sys/include/dev/ic/ahciregs.h @@ -34,8 +34,10 @@ #include <sys/param.h> struct hba_port { - volatile uint64_t clb; /* Command list base (1k-byte aligned) */ - volatile uint64_t fb; /* FIS base (256-byte aligned) */ + volatile uint32_t clb; /* Command list base low (1k-byte aligned) */ + volatile uint32_t clbu; /* Command list base upper */ + volatile uint32_t fb; /* FIS base (256-byte aligned) */ + volatile uint32_t fbu; /* FIS base upper */ volatile uint32_t is; /* Interrupt status */ volatile uint32_t ie; /* Interrupt enable */ volatile uint32_t cmd; /* Command and status */ @@ -86,6 +88,7 @@ struct hba_memspace { */ #define AHCI_PXSSTS_DET(SSTS) (SSTS & 0xF) #define AHCI_PXSSTS_IPM(SSTS) ((SSTS >> 8) & 0xF) +#define AHCI_PXSSTS_SPD(SSTS) ((SSTS >> 4) & 0xF) /* * Port SATA control bits @@ -98,6 +101,7 @@ struct hba_memspace { * See section 3.3.7 of the AHCI spec. */ #define AHCI_PXCMD_ST BIT(0) /* Start */ +#define AHCI_PXCMD_SUD BIT(1) /* Spin-up device */ #define AHCI_PXCMD_FRE BIT(4) /* FIS Receive Enable */ #define AHCI_PXCMD_FR BIT(14) /* FIS Receive Running */ #define AHCI_PXCMD_CR BIT(15) /* Command List Running */ @@ -122,6 +126,9 @@ struct hba_memspace { */ #define AHCI_CAP_NP(CAP) (CAP & 0x1F) /* Number of ports */ #define AHCI_CAP_NCS(CAP) ((CAP >> 8) & 0x1F) /* Number of command slots */ +#define AHCI_CAP_EMS(CAP) ((CAP >> 6) & 1) /* Enclosure management support */ +#define AHCI_CAP_SAL(CAP) ((CAP >> 25) & 1) /* Supports activity LED */ +#define AHCI_CAP_SSS(CAP) ((CAP >> 27) & 1) /* Supports staggered spin up */ /* * Device detection (DET) and Interface power @@ -132,6 +139,31 @@ struct hba_memspace { #define AHCI_DET_PRESENT 1 /* Device present (no PHY comm) */ #define AHCI_DET_COMM 3 /* Device present and phy comm established */ #define AHCI_IPM_ACTIVE 1 +#define AHCI_SPD_GEN1 1 /* 1.5 Gb/s */ +#define AHCI_SPD_GEN2 2 /* 3 Gb/s */ +#define AHCI_SPD_GEN3 3 /* 6 Gb/s */ + +/* + * PxSERR bits + * See section 3.3.12 of the AHCI spec + */ +#define AHCI_SERR_I BIT(0) /* Recovered data integrity error */ +#define AHCI_SERR_M BIT(1) /* Recovered comms error */ +#define AHCI_SERR_T BIT(8) /* Transient data integrity error */ +#define AHCI_SERR_C BIT(9) /* Persistent comms error */ +#define AHCI_SERR_P BIT(10) /* Protocol error ("oh fuck!" bit) */ +#define AHCI_SERR_E BIT(11) /* Internal error (only God knows, just pray) */ +#define AHCI_DIAG_N BIT(16) /* PhyRdy change */ +#define AHCI_DIAG_I BIT(17) /* PHY internal error */ +#define AHCI_DIAG_W BIT(18) /* Comm wake */ +#define AHCI_DIAG_B BIT(19) /* 10B to 8B decode error */ +#define AHCI_DIAG_C BIT(21) /* CRC error */ +#define AHCI_DIAG_H BIT(22) /* Handshake error */ +#define AHCI_DIAG_S BIT(23) /* Link sequence error */ +#define AHCI_DIAG_T BIT(24) /* Transport state transition error */ +#define AHCI_DIAG_F BIT(25) /* Unknown FIS type */ + +#define ATAPI_SIG 0xEB140101 /* * Device detection initialization values |