diff options
Diffstat (limited to 'sys/include/arch/amd64')
| -rw-r--r-- | sys/include/arch/amd64/bus.h | 8 | ||||
| -rw-r--r-- | sys/include/arch/amd64/cdefs.h | 10 | ||||
| -rw-r--r-- | sys/include/arch/amd64/cpu.h | 9 | ||||
| -rw-r--r-- | sys/include/arch/amd64/frame.h | 2 | ||||
| -rw-r--r-- | sys/include/arch/amd64/frameasm.h | 10 | ||||
| -rw-r--r-- | sys/include/arch/amd64/gdt.h | 79 | ||||
| -rw-r--r-- | sys/include/arch/amd64/intr.h | 52 | ||||
| -rw-r--r-- | sys/include/arch/amd64/ioapic.h | 3 | ||||
| -rw-r--r-- | sys/include/arch/amd64/isa/i8042var.h | 2 | ||||
| -rw-r--r-- | sys/include/arch/amd64/pci/pci.h | 40 | ||||
| -rw-r--r-- | sys/include/arch/amd64/syscall.h | 105 |
11 files changed, 282 insertions, 38 deletions
diff --git a/sys/include/arch/amd64/bus.h b/sys/include/arch/amd64/bus.h index 00cb3ba..25088b4 100644 --- a/sys/include/arch/amd64/bus.h +++ b/sys/include/arch/amd64/bus.h @@ -36,13 +36,7 @@ struct bus_resource; -/* - * Hyra assumes that the bootloader uses PDE[256] for some - * higher half mappings. To avoid conflicts with those mappings, - * this offset is used to start device memory at PDE[257]. This - * will give us more than enough space. - */ -#define MMIO_OFFSET (VM_HIGHER_HALF + 0x8000000000) +#define MMIO_OFFSET VM_HIGHER_HALF /* Resource signature size max */ #define RSIG_MAX 16 diff --git a/sys/include/arch/amd64/cdefs.h b/sys/include/arch/amd64/cdefs.h index 256fd8b..0a20324 100644 --- a/sys/include/arch/amd64/cdefs.h +++ b/sys/include/arch/amd64/cdefs.h @@ -41,5 +41,15 @@ #define md_pause() __ASMV("rep; nop") /* (F3 90) PAUSE */ #define md_intoff() __ASMV("cli") /* Clear interrupts */ #define md_inton() __ASMV("sti") /* Enable interrupts */ +#define md_hlt() __ASMV("hlt") /* Halt the processor */ + +/* + * AMD64 specific defines + */ +#define __invlpg(VA) \ + __ASMV("invlpg %0" \ + : \ + : "m" ((VA)) \ + : "memory") #endif /* !_AMD64_CDEFS_H_ */ diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h index ce42416..2d08d6e 100644 --- a/sys/include/arch/amd64/cpu.h +++ b/sys/include/arch/amd64/cpu.h @@ -33,6 +33,7 @@ #include <sys/types.h> #include <sys/cdefs.h> #include <sys/proc.h> +#include <sys/spinlock.h> #include <machine/tss.h> #define CPU_IRQ(IRQ_N) (BIT((IRQ_N)) & 0xFF) @@ -40,17 +41,25 @@ struct cpu_info { uint32_t apicid; uint8_t has_x2apic : 1; + uint8_t tlb_shootdown : 1; uint8_t ipl; size_t lapic_tmr_freq; uint8_t irq_mask; + vaddr_t shootdown_va; struct tss_entry *tss; struct proc *curtd; + struct spinlock lock; struct cpu_info *self; }; __dead void cpu_halt_all(void); +void cpu_halt_others(void); void cpu_startup(struct cpu_info *ci); +struct cpu_info *cpu_get(uint32_t index); +uint32_t cpu_count(void); +void cpu_shootdown_tlb(vaddr_t va); + struct cpu_info *this_cpu(void); void mp_bootstrap_aps(struct cpu_info *ci); diff --git a/sys/include/arch/amd64/frame.h b/sys/include/arch/amd64/frame.h index 31dcdef..2bd9a7c 100644 --- a/sys/include/arch/amd64/frame.h +++ b/sys/include/arch/amd64/frame.h @@ -58,4 +58,6 @@ struct trapframe { uint64_t ss; }; +#define TF_IP(TFP) ((TFP)->rip) + #endif /* !_MACHINE_FRAME_H_ */ diff --git a/sys/include/arch/amd64/frameasm.h b/sys/include/arch/amd64/frameasm.h index 22217eb..4dc075e 100644 --- a/sys/include/arch/amd64/frameasm.h +++ b/sys/include/arch/amd64/frameasm.h @@ -30,6 +30,8 @@ #ifndef _MACHINE_FRAMEASM_H_ #define _MACHINE_FRAMEASM_H_ +#define ALIGN_TEXT .align 8, 0x90 + /* * If the interrupt has an error code, this macro shall * be used to create the trapframe. @@ -121,6 +123,7 @@ */ #define TRAPENTRY_EC(ENTLABEL, TRAPNO) \ ENTLABEL: ; \ + cli ; \ testq $0x3, 16(%rsp) ; \ jz 1f ; \ lfence ; \ @@ -133,7 +136,8 @@ jz 2f ; \ lfence ; \ swapgs ; \ - 2: iretq + 2: sti ; \ + iretq /* * Trap entry where no error code is on @@ -141,6 +145,7 @@ */ #define TRAPENTRY(ENTLABEL, TRAPNO) \ ENTLABEL: ; \ + cli ; \ testq $0x3, 8(%rsp) ; \ jz 1f ; \ lfence ; \ @@ -153,6 +158,7 @@ jz 2f ; \ lfence ; \ swapgs ; \ - 2: iretq + 2: sti ; \ + iretq #endif /* !_MACHINE_FRAMEASM_H_ */ diff --git a/sys/include/arch/amd64/gdt.h b/sys/include/arch/amd64/gdt.h index f87416f..0c5faf1 100644 --- a/sys/include/arch/amd64/gdt.h +++ b/sys/include/arch/amd64/gdt.h @@ -4,18 +4,48 @@ #include <sys/types.h> #include <sys/cdefs.h> +#define GDT_TSS_INDEX 5 +#define GDT_ENTRY_COUNT 7 + +/* Segment selectors */ #define KERNEL_CS 0x08 #define KERNEL_DS 0x10 -#define USER_CS 0x18 -#define USER_DS 0x20 -#define GDT_TSS 5 +#define USER_CS 0x18 +#define USER_DS 0x20 + +/* + * Bit definitions for regular segment descriptors + * + * See Intel SPG 3/25 Section 3.4.5 - Segment Descriptors + */ + +#define GDT_ATTRIBUTE_ACCESSED BIT(0) /* Accessed */ +#define GDT_ATTRIBUTE_EXECUTABLE BIT(3) /* Executable */ +#define GDT_ATTRIBUTE_NONSYSTEM BIT(4) /* Code/data */ +#define GDT_ATTRIBUTE_PRESENT BIT(7) /* Present */ +#define GDT_ATTRIBUTE_64BIT_CODE BIT(13) /* 64-bit code */ +#define GDT_ATTRIBUTE_32BIT BIT(14) /* 32-bit code/data */ +#define GDT_ATTRIBUTE_GRANULARITY BIT(15) /* 4KiB limit granularity */ + +/* Attributes for executable segments */ +#define GDT_ATTRIBUTE_READABLE BIT(1) /* Readable */ +#define GDT_ATTRIBUTE_CONFORMING BIT(2) /* Conforming */ + +/* Attributes for non-executable segments */ +#define GDT_ATTRIBUTE_WRITABLE BIT(1) /* Writable */ +#define GDT_ATTRIBUTE_EXPANDS_DOWN BIT(2) /* See SPG 3/25 Section 6.8.1 */ + +/* DPL (Descriptor Privilege Level) specifier */ +#define GDT_ATTRIBUTE_DPL0 0 +#define GDT_ATTRIBUTE_DPL1 (1 << 5) +#define GDT_ATTRIBUTE_DPL2 (2 << 5) +#define GDT_ATTRIBUTE_DPL3 (3 << 5) struct __packed gdt_entry { uint16_t limit; uint16_t base_low; uint8_t base_mid; - uint8_t access; - uint8_t granularity; + uint16_t attributes; uint8_t base_hi; }; @@ -24,27 +54,28 @@ struct __packed gdtr { uintptr_t offset; }; +extern struct gdt_entry g_gdt_data[GDT_ENTRY_COUNT]; +extern const struct gdtr g_gdtr; + __always_inline static inline void -gdt_load(struct gdtr *gdtr) +gdt_load(void) { - __ASMV("lgdt %0\n" - "push $8\n" /* Push CS */ - "lea 1f(%%rip), %%rax\n" /* Load 1 label address into RAX */ - "push %%rax\n" /* Push the return address (label 1) */ - "lretq\n" /* Far return to update CS */ - "1:\n" - " mov $0x10, %%eax\n" - " mov %%eax, %%ds\n" - " mov %%eax, %%es\n" - " mov %%eax, %%fs\n" - " mov %%eax, %%gs\n" - " mov %%eax, %%ss\n" - : - : "m" (*gdtr) - : "rax", "memory" - ); + __ASMV("lgdt %0\n" + "push %1\n" /* Push code segment selector */ + "lea 1f(%%rip), %%rax\n" /* Load label 1 address into RAX */ + "push %%rax\n" /* Push return address (label 1) */ + "lretq\n" /* Far return to update CS */ + "1:\n" + " mov %2, %%ax\n" /* Load data segment selectors */ + " mov %%ax, %%ds\n" + " mov %%ax, %%es\n" + " mov %%ax, %%fs\n" + " mov %%ax, %%gs\n" + " mov %%ax, %%ss\n" + : + : "m" (g_gdtr), "i"(KERNEL_CS), "i"(KERNEL_DS) + : "rax", "memory" + ); } -extern struct gdt_entry g_gdt_data[256]; - #endif /* !AMD64_GDT_H_ */ diff --git a/sys/include/arch/amd64/intr.h b/sys/include/arch/amd64/intr.h index c643945..c848b6f 100644 --- a/sys/include/arch/amd64/intr.h +++ b/sys/include/arch/amd64/intr.h @@ -47,11 +47,59 @@ #define IPL_CLOCK 2 /* Clock */ #define IPL_HIGH 3 /* Defer everything */ -struct intr_entry { +struct intr_hand; + +/* + * Contains information passed to driver + * + * @ihp: Interrupt handler + * @data: Driver specific data + */ +struct intr_data { + struct intr_hand *ihp; + union { + void *data; + uint64_t data_u64; + }; +}; + +/* + * Interrupt handler + * + * [r]: Required for intr_register() + * [o]: Not required for intr_register() + * [v]: Returned by intr_register() + * + * @func: The actual handler [r] + * @data: Interrupt data [o/v] + * @name: Interrupt name [v] + * @priority: Interrupt priority [r] + * @irq: Interrupt request number [o] + * @vector: Interrupt vector [v] + * + * XXX: `name' must be null terminated ('\0') + * + * XXX: `irq` can be set to -1 for MSI/MSI-X + * interrupts. + * + * XXX: `func` must be the first field in this + * structure so that it may be called through + * assembly. + * + * XXX: `ist' should usually be set to -1 but can be + * used if an interrupt requires its own stack. + */ +struct intr_hand { + int(*func)(void *); + struct intr_data data; + char *name; int priority; + int irq; + int vector; }; -int intr_alloc_vector(const char *name, uint8_t priority); +void *intr_register(const char *name, const struct intr_hand *ih); + int splraise(uint8_t s); void splx(uint8_t s); diff --git a/sys/include/arch/amd64/ioapic.h b/sys/include/arch/amd64/ioapic.h index c11a85c..4cae800 100644 --- a/sys/include/arch/amd64/ioapic.h +++ b/sys/include/arch/amd64/ioapic.h @@ -31,7 +31,8 @@ #define _MACHINE_IOAPIC_H_ #include <sys/types.h> -#include <dev/acpi/tables.h> + +struct ioapic; void ioapic_init(struct ioapic *p); void ioapic_gsi_mask(uint8_t gsi); diff --git a/sys/include/arch/amd64/isa/i8042var.h b/sys/include/arch/amd64/isa/i8042var.h index ebd96ad..13c3095 100644 --- a/sys/include/arch/amd64/isa/i8042var.h +++ b/sys/include/arch/amd64/isa/i8042var.h @@ -82,7 +82,5 @@ void i8042_quirk(int mask); /* Internal - do not use */ void i8042_sync(void); -void i8042_kb_isr(void); -void i8042_kb_event(void); #endif /* _I8042VAR_H_ */ diff --git a/sys/include/arch/amd64/pci/pci.h b/sys/include/arch/amd64/pci/pci.h new file mode 100644 index 0000000..189a423 --- /dev/null +++ b/sys/include/arch/amd64/pci/pci.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_PCI_H_ +#define _MACHINE_PCI_H_ + +#include <sys/types.h> +#include <sys/cdefs.h> +#include <dev/pci/pci.h> + +__weak pcireg_t md_pci_readl(struct pci_device *dev, uint32_t off); +__weak void md_pci_writel(struct pci_device *dev, uint32_t off, pcireg_t val); + +#endif /* !_MACHINE_PCI_H_ */ diff --git a/sys/include/arch/amd64/syscall.h b/sys/include/arch/amd64/syscall.h new file mode 100644 index 0000000..cc401e9 --- /dev/null +++ b/sys/include/arch/amd64/syscall.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_SYSCALL_H_ +#define _MACHINE_SYSCALL_H_ + +#if !defined(__ASSEMBLER__) +__always_inline static inline long +syscall0(uint64_t code) +{ + volatile long ret; + __ASMV("int $0x80" : "=a"(ret) : "a"(code)); + return ret; +} + +__always_inline static inline long +syscall1(uint64_t code, uint64_t arg0) +{ + volatile long ret; + __ASMV("int $0x80" : "=a"(ret) : "a"(code), "D"(arg0) : "memory"); + return ret; +} + +__always_inline static long inline +syscall2(uint64_t code, uint64_t arg0, uint64_t arg1) +{ + volatile long ret; + __ASMV("int $0x80" : "=a"(ret) : "a"(code), "D"(arg0), "S"(arg1) : "memory"); + return ret; +} + +__always_inline static inline long +syscall3(uint64_t code, uint64_t arg0, uint64_t arg1, uint64_t arg2) +{ + volatile long ret; + __ASMV("int $0x80" : "=a"(ret) : "a"(code), "D"(arg0), "S"(arg1), "d"(arg2) : "memory"); + return ret; +} + +__always_inline static inline long +syscall4(uint64_t code, uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3) +{ + volatile long ret; + register uint64_t _arg3 asm("r10") = arg3; + __ASMV("int $0x80" : "=a"(ret) : "a"(code), "D"(arg0), "S"(arg1), "d"(arg2), "r"(_arg3) : "memory"); + return ret; +} + +__always_inline static inline long +syscall5(uint64_t code, uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4) +{ + volatile long ret; + register uint64_t _arg3 asm("r10") = arg3; + register uint64_t _arg4 asm("r9") = arg4; + __ASMV("int $0x80" : "=a"(ret) : "a"(code), "D"(arg0), "S"(arg1), "d"(arg2), "r"(_arg3), "r"(_arg4) : "memory"); + return ret; +} + +__always_inline static inline long +syscall6(uint64_t code, uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5) +{ + volatile long ret; + register uint64_t _arg3 asm("r10") = arg3; + register uint64_t _arg4 asm("r9") = arg4; + register uint64_t _arg5 asm("r8") = arg5; + __ASMV("int $0x80" : "=a"(ret) : "a"(code), "D"(arg0), "S"(arg1), "d"(arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5) : "memory"); + return ret; +} + +#define _SYSCALL_N(a0, a1, a2, a3, a4, a5, a6, name, ...) \ + name + +#define syscall(...) \ +_SYSCALL_N(__VA_ARGS__, syscall6, syscall5, \ + syscall4, syscall3, syscall2, syscall1, \ + syscall0)(__VA_ARGS__) + +#endif /* !__ASSEMBLER__ */ +#endif /* !_MACHINE_SYSCALL_H_ */ |