diff options
Diffstat (limited to 'sys/include/arch/amd64')
| -rw-r--r-- | sys/include/arch/amd64/asm.h | 10 | ||||
| -rw-r--r-- | sys/include/arch/amd64/cpu.h | 18 | ||||
| -rw-r--r-- | sys/include/arch/amd64/intr.h | 3 | ||||
| -rw-r--r-- | sys/include/arch/amd64/ipi.h | 109 | ||||
| -rw-r--r-- | sys/include/arch/amd64/tsc.h | 55 |
5 files changed, 193 insertions, 2 deletions
diff --git a/sys/include/arch/amd64/asm.h b/sys/include/arch/amd64/asm.h index 8d2c812..aca49d2 100644 --- a/sys/include/arch/amd64/asm.h +++ b/sys/include/arch/amd64/asm.h @@ -34,6 +34,16 @@ #include <sys/param.h> #include <machine/msr.h> +/* CR4 bits */ +#define CR4_TSD BIT(2) /* Timestamp disable */ +#define CR4_DE BIT(3) /* Debugging extensions */ +#define CR4_PSE BIT(4) /* Page size extensions */ +#define CR4_PCE BIT(8) /* Performance monitoring counter enable */ +#define CR4_UMIP BIT(11) /* User mode instruction prevention */ +#define CR4_LA57 BIT(12) /* Level 5 paging enable */ +#define CR4_VMXE BIT(13) /* Virtual machine extensions enable */ +#define CR4_SMXE BIT(14) /* Safer mode extensions enable */ + /* * Contains information for the current * core. Stored in %GS. diff --git a/sys/include/arch/amd64/cpu.h b/sys/include/arch/amd64/cpu.h index 116661b..6ed675e 100644 --- a/sys/include/arch/amd64/cpu.h +++ b/sys/include/arch/amd64/cpu.h @@ -37,16 +37,30 @@ #include <sys/spinlock.h> #include <machine/tss.h> #include <machine/cdefs.h> +#include <machine/intr.h> #define CPU_IRQ(IRQ_N) (BIT((IRQ_N)) & 0xFF) /* Feature bits */ -#define CPU_FEAT_SMAP BIT(0) -#define CPU_FEAT_SMEP BIT(1) +#define CPU_FEAT_SMAP BIT(0) +#define CPU_FEAT_SMEP BIT(1) +#define CPU_FEAT_UMIP BIT(2) +#define CPU_FEAT_TSCINV BIT(3) /* TSC invariant */ + +/* CPU vendors */ +#define CPU_VENDOR_OTHER 0x00000000 +#define CPU_VENDOR_INTEL 0x00000001 +#define CPU_VENDOR_AMD 0x00000002 + +typedef uint16_t ipi_pend_t; struct cpu_info { uint32_t apicid; uint32_t feat; + uint32_t vendor; /* Vendor (see CPU_VENDOR_*) */ + uint8_t ipi_dispatch : 1; /* 1: IPIs being dispatched */ + uint8_t ipi_id; + ipi_pend_t ipi_pending[N_IPIVEC]; uint8_t id; /* MI Logical ID */ uint8_t model : 4; /* CPU model number */ uint8_t family : 4; /* CPU family ID */ diff --git a/sys/include/arch/amd64/intr.h b/sys/include/arch/amd64/intr.h index 3870f18..6d9bb09 100644 --- a/sys/include/arch/amd64/intr.h +++ b/sys/include/arch/amd64/intr.h @@ -48,6 +48,9 @@ #define IPL_CLOCK 2 /* Clock */ #define IPL_HIGH 3 /* Defer everything */ +#define N_IPIVEC 4 /* Number of vectors reserved for IPIs */ +#define IPI_PER_VEC 16 /* Max IPIs per vector */ + struct intr_hand; /* diff --git a/sys/include/arch/amd64/ipi.h b/sys/include/arch/amd64/ipi.h new file mode 100644 index 0000000..1a3b51c --- /dev/null +++ b/sys/include/arch/amd64/ipi.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_IPI_H_ +#define _MACHINE_IPI_H_ + +#include <sys/types.h> +#include <machine/cpu.h> +#include <machine/lapic.h> + +/* Fixed IPI IDs */ +#define IPI_HALT 0 +#define IPI_TLB 1 + +/* + * Represents an interprocessor interrupt + * handler. + * + * @cookie: Used to verifying an instance + * @id: IPI ID (identifies the IPI) + * @mask: If set, IPIs are ignored + * @handler: Handler routine + */ +struct cpu_ipi { + uint16_t cookie; + uint8_t id; + int(*handler)(struct cpu_ipi *ipi); +}; + +/* + * Represents an interrupt vector for a + * specific IPI + * + * @ipi: IPIs associated with this vector + * @cookie: Used to verify an instance + * @nipi: Number of IPIs associated + * @vec: System interrupt vector number + */ +struct ipi_vector { + struct cpu_ipi ipi[IPI_PER_VEC]; + uint16_t cookie; + uint8_t nipi; + uint8_t vec; +}; + +int md_ipi_alloc(struct cpu_ipi **res); +int md_ipi_send(struct cpu_info *ci); +void md_ipi_init(void); + +/* + * Get the vector an IPI belongs to + * + * @ipi: IPI to check + */ +__always_inline static inline uint8_t +ipi_vector(uint8_t ipi) +{ + return ipi / N_IPIVEC; +} + +/* + * Get the handler index an IPI belongs + * to + * + * @ipi: IPI to check + */ +__always_inline static inline uint8_t +ipi_index(uint8_t ipi) +{ + return ipi % (sizeof(ipi_pend_t) * 8); +} + +__always_inline static inline int +cpu_ipi_send(struct cpu_info *ci, uint8_t ipi) +{ + uint8_t vec = ipi_vector(ipi); + uint8_t idx = ipi_index(ipi); + + ci->ipi_pending[vec] |= BIT(idx); + return md_ipi_send(ci); +} + +#endif /* !_MACHINE_IPI_H_ */ diff --git a/sys/include/arch/amd64/tsc.h b/sys/include/arch/amd64/tsc.h new file mode 100644 index 0000000..d9eed4f --- /dev/null +++ b/sys/include/arch/amd64/tsc.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Hyra nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_TSC_H_ +#define _MACHINE_TSC_H_ + +#include <sys/types.h> +#include <sys/cdefs.h> +#include <sys/param.h> + +uint64_t rdtsc_rel(void); + +__always_inline static inline uint64_t +rdtsc(void) +{ + uint32_t lo, hi; + + __ASMV( + "rdtsc" + : "=d" (hi), + "=a" (lo) + : + : "memory" + ); + + return COMBINE32(hi, lo); +} + +#endif /* !_MACHINE_TSC_H_ */ |