4 files changed, 79 insertions, 5 deletions
diff --git a/sys/arch/amd64/amd64/machdep.c b/sys/arch/amd64/amd64/machdep.c
index 94b2d18..72de150 100644
--- a/sys/arch/amd64/amd64/machdep.c
+++ b/sys/arch/amd64/amd64/machdep.c
@@ -609,6 +609,7 @@ cpu_startup(struct cpu_info *ci)
 
     try_mitigate_spectre();
     ci->online = 1;
+    ci->preempt  = 1;
 
     cpu_get_info(ci);
     cpu_enable_smep();
diff --git a/sys/arch/amd64/amd64/proc_machdep.c b/sys/arch/amd64/amd64/proc_machdep.c
index a1d6563..82b4e4f 100644
--- a/sys/arch/amd64/amd64/proc_machdep.c
+++ b/sys/arch/amd64/amd64/proc_machdep.c
@@ -264,6 +264,36 @@ sched_switch_to(struct trapframe *tf, struct proc *td)
 }
 
 /*
+ * Enable or disable preemption on the current
+ * processor
+ *
+ * @enable: Enable preemption if true
+ */
+void
+sched_preempt_set(bool enable)
+{
+    struct cpu_info *ci = this_cpu();
+
+    if (ci == NULL) {
+        return;
+    }
+
+    ci->preempt = enable;
+}
+
+bool
+sched_preemptable(void)
+{
+    struct cpu_info *ci = this_cpu();
+
+    if (ci == NULL) {
+        return false;
+    }
+
+    return ci->preempt;
+}
+
+/*
  * Perform a context switch.
  */
 void
@@ -273,6 +303,11 @@ md_sched_switch(struct trapframe *tf)
     struct cpu_info *ci;
 
     ci = this_cpu();
+    if (!ci->preempt) {
+        sched_oneshot(false);
+        return;
+    }
+
     td = ci->curtd;
     mi_sched_switch(td);
 
diff --git a/sys/arch/amd64/amd64/reboot.c b/sys/arch/amd64/amd64/reboot.c
index d47a352..8ebe15e 100644
--- a/sys/arch/amd64/amd64/reboot.c
+++ b/sys/arch/amd64/amd64/reboot.c
@@ -34,9 +34,49 @@
 #include <machine/cpu.h>
 #include <dev/acpi/acpi.h>
 
+static void
+cpu_reset_intel(struct cpu_info *ci)
+{
+    /*
+     * Ivy bridge processors and their panther point chipsets
+     * (family 6) can be reset through special PCH reset control
+     * registers
+     */
+    if (ci->family == 6) {
+        outb(0xCF9, 3 << 1);
+    }
+}
+
+/*
+ * Attempt to reboot the system, we do this in many
+ * stages of escalation. If a reset via the i8042
+ * controller fails and we are on an Intel processor,
+ * attempt a chipset specific reset. If that somehow fails
+ * as well, just smack the cpu with a NULL IDTR as well
+ * as an INT $0x0
+ */
+static void
+__cpu_reset(struct cpu_info *ci)
+{
+    /* Try via the i8042 */
+    outb(0x64, 0xFE);
+
+    /* Something went wrong if we are here */
+    if (ci == NULL) {
+        return;
+    }
+
+    if (ci->vendor == CPU_VENDOR_INTEL) {
+        cpu_reset_intel(ci);
+    }
+}
+
 void
 cpu_reboot(int method)
 {
+    struct cpu_info *ci = this_cpu();
+    uint32_t *__dmmy = NULL;
+
     if (ISSET(method, REBOOT_POWEROFF)) {
         acpi_sleep(ACPI_SLEEP_S5);
     }
@@ -45,10 +85,9 @@ cpu_reboot(int method)
         cpu_halt_all();
     }
 
-    /* Pulse the reset line until the machine goes down */
-    for (;;) {
-        outb(0x64, 0xFE);
-    }
+    __cpu_reset(ci);
+    asm volatile("lgdt %0; int $0x0" :: "m" (__dmmy));
+    __builtin_unreachable();
 }
 
 /*
diff --git a/sys/arch/amd64/isa/i8042.c b/sys/arch/amd64/isa/i8042.c
index eae3c32..095f1f4 100644
--- a/sys/arch/amd64/isa/i8042.c
+++ b/sys/arch/amd64/isa/i8042.c
@@ -89,7 +89,6 @@ static struct i8042_databuf i8042_etab[] = {
     }
 };
 
-static struct spinlock data_lock;
 static struct spinlock isr_lock;
 static bool shift_key = false;
 static bool capslock = false;