1 files changed, 26 insertions, 8 deletions
diff --git a/sys/arch/amd64/pci/pci_machdep.c b/sys/arch/amd64/pci/pci_machdep.c
index 1cc2162..5b49a78 100644
--- a/sys/arch/amd64/pci/pci_machdep.c
+++ b/sys/arch/amd64/pci/pci_machdep.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024 Ian Marco Moffett and the Osmora Team.
+ * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -33,11 +33,13 @@
 #include <sys/mmio.h>
 #include <dev/pci/pci.h>
 #include <dev/pci/pciregs.h>
+#include <machine/pci/pci.h>
 #include <machine/pio.h>
 #include <machine/bus.h>
 #include <machine/cpu.h>
 #include <machine/intr.h>
 #include <machine/idt.h>
+#include <machine/lapic.h>
 
 /* Base address masks for BARs */
 #define PCI_BAR_MEMMASK ~7
@@ -72,8 +74,8 @@ pci_get_barreg(struct pci_device *dev, uint8_t bar)
     }
 }
 
-pcireg_t
-pci_readl(struct pci_device *dev, uint32_t offset)
+__weak pcireg_t
+md_pci_readl(struct pci_device *dev, uint32_t offset)
 {
     uint32_t address;
 
@@ -82,8 +84,8 @@ pci_readl(struct pci_device *dev, uint32_t offset)
     return inl(0xCFC) >> ((offset & 3) * 8);
 }
 
-void
-pci_writel(struct pci_device *dev, uint32_t offset, pcireg_t val)
+__weak void
+md_pci_writel(struct pci_device *dev, uint32_t offset, pcireg_t val)
 {
     uint32_t address;
 
@@ -140,6 +142,16 @@ pci_map_bar(struct pci_device *dev, uint8_t barno, void **vap)
     return bus_map(bar, size, 0, vap);
 }
 
+void
+pci_msix_eoi(void)
+{
+    /*
+     * On AMD64 all we need to do is send an EOI to the
+     * Local APIC onboard the current processor.
+     */
+    lapic_eoi();
+}
+
 /*
  * Enable MSI-X for a device and allocate an
  * interrupt vector.
@@ -152,6 +164,7 @@ pci_enable_msix(struct pci_device *dev, const struct msi_intr *intr)
 {
     volatile uint64_t *tbl;
     struct cpu_info *ci;
+    struct intr_hand ih, *ih_res;
     uint32_t data, msg_ctl;
     uint64_t msg_addr, tmp;
     uint16_t tbl_off;
@@ -173,9 +186,14 @@ pci_enable_msix(struct pci_device *dev, const struct msi_intr *intr)
     tbl = (void *)((dev->bar[bir] & PCI_BAR_MEMMASK) + MMIO_OFFSET);
     tbl = (void *)((char *)tbl + tbl_off);
 
-    /* Get the vector and setup handler */
-    vector = intr_alloc_vector(intr->name, IPL_BIO);
-    idt_set_desc(vector, IDT_INT_GATE, ISR(intr->handler), 0);
+    ih.func = intr->handler;
+    ih.priority = IPL_BIO;
+    ih.irq = -1;
+    ih_res = intr_register(intr->name, &ih);
+    if (ih_res == NULL) {
+        return -EIO;
+    }
+    vector = ih_res->vector;
 
     /*
      * Setup the message data at bits 95:64 of the message