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-rw-r--r--sys/arch/aarch64/aarch64/exception.c128
-rw-r--r--sys/arch/aarch64/aarch64/intr.c37
-rw-r--r--sys/arch/aarch64/aarch64/locore.S36
-rw-r--r--sys/arch/aarch64/aarch64/machdep.c21
-rw-r--r--sys/arch/aarch64/aarch64/pmap.c280
-rw-r--r--sys/arch/aarch64/aarch64/proc_machdep.c6
-rw-r--r--sys/arch/aarch64/aarch64/reboot.c18
-rw-r--r--sys/arch/aarch64/aarch64/vector.S96
-rw-r--r--sys/arch/aarch64/conf/GENERIC9
-rw-r--r--sys/arch/aarch64/conf/link.ld6
-rw-r--r--sys/arch/aarch64/pci/pci_machdep.c14
11 files changed, 625 insertions, 26 deletions
diff --git a/sys/arch/aarch64/aarch64/exception.c b/sys/arch/aarch64/aarch64/exception.c
new file mode 100644
index 0000000..d6f1f97
--- /dev/null
+++ b/sys/arch/aarch64/aarch64/exception.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/syslog.h>
+#include <sys/param.h>
+#include <sys/cdefs.h>
+#include <machine/cdefs.h>
+#include <machine/exception.h>
+
+#define pr_trace(fmt, ...) kprintf("exception: " fmt, ##__VA_ARGS__)
+#define pr_error(...) pr_trace(__VA_ARGS__)
+
+static inline void
+log_esr_class(uint8_t class)
+{
+ switch (class) {
+ case EC_WF:
+ pr_error("trapped WF\n");
+ break;
+ case EC_MCRMRC:
+ pr_error("trapped MCR/MRC\n");
+ break;
+ case EC_MCRRC:
+ pr_trace("trapped MCRR/MRRC\n");
+ break;
+ case EC_LDCSTC:
+ pr_error("trapped LDC/STC\n");
+ break;
+ case EC_SVE:
+ pr_trace("trapped SVE/SIMD/FP operation\n");
+ break;
+ case EC_BRE:
+ pr_error("ibt: bad branch target\n");
+ break;
+ case EC_ILLX:
+ pr_error("illegal execution state\n");
+ break;
+ case EC_SVC64:
+ /* TODO */
+ pr_error("supervisor call (TODO)!!\n");
+ break;
+ case EC_PCALIGN:
+ pr_error("PC alignment fault\n");
+ break;
+ case EC_DABORT:
+ case EC_EDABORT:
+ pr_error("data abort\n");
+ break;
+ case EC_SPALIGN:
+ pr_error("SP alignment fault\n");
+ break;
+ case EC_SERR:
+ pr_error("system error\n");
+ break;
+ default:
+ pr_error("unknown exception\n");
+ }
+}
+
+static void
+regdump(struct trapframe *tf, uint64_t elr)
+{
+ kprintf(OMIT_TIMESTAMP
+ "X0=%p X1=%p X2=%p\n"
+ "X3=%p X4=%p X5=%p\n"
+ "X6=%p X7=%p X8=%p\n"
+ "X9=%p X10=%p X11=%p\n"
+ "X12=%p X13=%p X14=%p\n"
+ "X15=%p X16=%p X17=%p\n"
+ "X18=%p X19=%p X20=%p\n"
+ "X21=%p X22=%p X23=%p\n"
+ "X24=%p X25=%p X26=%p\n"
+ "X27=%p X28=%p X29=%p\n"
+ "X30=%p\n"
+ "ELR=%p\n",
+ tf->x0, tf->x1, tf->x2, tf->x3,
+ tf->x4, tf->x5, tf->x6, tf->x7,
+ tf->x8, tf->x9, tf->x10, tf->x11,
+ tf->x12, tf->x13, tf->x14, tf->x15,
+ tf->x16, tf->x17, tf->x18, tf->x19,
+ tf->x20, tf->x21, tf->x22, tf->x23,
+ tf->x24, tf->x25, tf->x26, tf->x27,
+ tf->x28, tf->x29, tf->x30, elr);
+}
+
+/*
+ * Handle an exception
+ *
+ * @esr: Copy of the Exception Syndrome Register
+ */
+void
+handle_exception(struct trapframe *tf)
+{
+ uint8_t class;
+
+ class = (tf->esr >> 26) & 0x3F;
+ log_esr_class(class);
+ regdump(tf, tf->elr);
+ for (;;) {
+ md_hlt();
+ }
+}
diff --git a/sys/arch/aarch64/aarch64/intr.c b/sys/arch/aarch64/aarch64/intr.c
new file mode 100644
index 0000000..5fd2439
--- /dev/null
+++ b/sys/arch/aarch64/aarch64/intr.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/intr.h>
+
+void *
+intr_register(const char *name, const struct intr_hand *ih)
+{
+ /* TODO: Stub */
+ return NULL;
+}
diff --git a/sys/arch/aarch64/aarch64/locore.S b/sys/arch/aarch64/aarch64/locore.S
new file mode 100644
index 0000000..2155991
--- /dev/null
+++ b/sys/arch/aarch64/aarch64/locore.S
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ .text
+ .globl md_cpu_init
+md_cpu_init:
+ ldr x0, =__vectab
+ msr vbar_el1, x0
+ ret
+
diff --git a/sys/arch/aarch64/aarch64/machdep.c b/sys/arch/aarch64/aarch64/machdep.c
index a29ad7e..33d7c42 100644
--- a/sys/arch/aarch64/aarch64/machdep.c
+++ b/sys/arch/aarch64/aarch64/machdep.c
@@ -34,8 +34,10 @@
struct cpu_info g_bsp_ci = {0};
+void md_cpu_init(void);
+
void
-cpu_startup(struct cpu_info *ci)
+cpu_halt_others(void)
{
/* TODO: STUB */
return;
@@ -69,6 +71,13 @@ md_sync_all(void)
return 0;
}
+void
+cpu_halt_all(void)
+{
+ /* TODO: Stub */
+ for (;;);
+}
+
/*
* Get the descriptor for the currently
* running processor.
@@ -78,6 +87,14 @@ this_cpu(void)
{
struct cpu_info *ci;
- __ASMV("mrs %0, tpidr_el0" : "=r" (ci));
+ __ASMV("mrs %0, tpidr_el1" : "=r" (ci));
return ci;
}
+
+void
+cpu_startup(struct cpu_info *ci)
+{
+ ci->self = ci;
+ __ASMV("msr tpidr_el1, %0" :: "r" (ci));
+ md_cpu_init();
+}
diff --git a/sys/arch/aarch64/aarch64/pmap.c b/sys/arch/aarch64/aarch64/pmap.c
index b5ebda9..870ef80 100644
--- a/sys/arch/aarch64/aarch64/pmap.c
+++ b/sys/arch/aarch64/aarch64/pmap.c
@@ -28,35 +28,274 @@
*/
#include <sys/types.h>
+#include <sys/cdefs.h>
+#include <sys/param.h>
+#include <sys/panic.h>
#include <machine/vas.h>
#include <vm/pmap.h>
+#include <vm/physmem.h>
+#include <vm/vm.h>
+
+/* Memory types for MAIR_ELx */
+#define MT_NORMAL 0x00
+#define MT_NORMAL_UC 0x02
+#define MT_DEVICE 0x03
+
+/* Memory attributes */
+#define MEM_DEV_NGNRNE 0x00
+#define MEM_DEV_NVNRE 0x04
+#define MEM_NORMAL_UC 0x44
+#define MEM_NORMAL 0xFF
+
+#define MT_ATTR(idx, attr) ((attr) << (8 * (idx)))
+
+/*
+ * Descriptor bits for page table entries
+ *
+ * @PTE_VALID: Must be set to be valid
+ * @PTE_TABLE: Table (1), block (0)
+ * @PTE_USER: User access allowed
+ * @PTE_READONLY: Read-only
+ * @PTE_ISH: Inner sharable
+ * @PTE_AF: Accessed flag
+ * @PTE_XN: Execute never
+ */
+#define PTE_ADDR_MASK 0x0000FFFFFFFFF000
+#define PTE_VALID BIT(0)
+#define PTE_TABLE BIT(1)
+#define PTE_USER BIT(6)
+#define PTE_READONLY BIT(7)
+#define PTE_ISH (3 << 8)
+#define PTE_AF BIT(10)
+#define PTE_XN BIT(54)
+
+/*
+ * Write the EL1 Memory Attribute Indirection
+ * Register.
+ *
+ * @val: Value to write
+ *
+ * XXX: Refer to the ARMv8 Reference Manual section
+ * D7.2.70
+ */
+static inline void
+mair_el1_write(uint64_t val)
+{
+ __ASMV("msr mair_el1, %0"
+ :
+ : "r" (val)
+ : "memory"
+ );
+}
+
+static inline void
+tlb_flush(vaddr_t va)
+{
+ __ASMV(
+ "tlbi vaae1is, %0\n"
+ "dsb ish\n"
+ "isb\n"
+ :
+ : "r" (va >> 12)
+ : "memory"
+ );
+}
+
+static uint64_t
+pmap_prot_to_pte(vm_prot_t prot)
+{
+ uint64_t pte_flags = 0;
+
+ pte_flags |= (PTE_VALID | PTE_TABLE | PTE_AF);
+ pte_flags |= (PTE_XN | PTE_READONLY | PTE_ISH);
+
+ if (ISSET(prot, PROT_WRITE))
+ pte_flags &= ~PTE_READONLY;
+ if (ISSET(prot, PROT_EXEC))
+ pte_flags &= ~PTE_XN;
+ if (ISSET(prot, PROT_USER))
+ pte_flags |= PTE_USER;
+
+ return pte_flags;
+}
+
+/*
+ * Returns an index for a specific page map
+ * label based on an input address.
+ */
+static size_t
+pmap_level_idx(vaddr_t ia, uint8_t level)
+{
+ switch (level) {
+ case 0: return (ia >> 39) & 0x1FF;
+ case 1: return (ia >> 30) & 0x1FF;
+ case 2: return (ia >> 21) & 0x1FF;
+ case 3: return (ia >> 12) & 0x1FF;
+ default: panic("pmap_level_idx: bad index\n");
+ }
+
+ __builtin_unreachable();
+}
+
+/*
+ * Extract a level from a pagemap
+ *
+ * @level: Current pagemap level
+ * @ia: Input virtual address
+ * @pmap: Current level to extract from
+ * @alloc: Set to true to allocate new entries
+ *
+ * XXX: `level_idx' can be grabbed with pmap_level_idx().
+ */
+static uintptr_t *
+pmap_extract(uint8_t level, vaddr_t ia, vaddr_t *pmap, bool alloc)
+{
+ uintptr_t next, level_alloc;
+ uint8_t idx;
+
+ if (pmap == NULL) {
+ return NULL;
+ }
+
+ idx = pmap_level_idx(ia, level);
+ next = pmap[idx];
+
+ if (ISSET(next, PTE_VALID)) {
+ next = next & PTE_ADDR_MASK;
+ return PHYS_TO_VIRT(next);
+ }
+
+ /*
+ * Nothing to grab at this point, we'll need to
+ * allocate our own entry. However, if we are
+ * told not to allocate anything, just return
+ * NULL.
+ */
+ if (!alloc) {
+ return NULL;
+ }
+
+ level_alloc = vm_alloc_frame(1);
+ if (level_alloc == 0) {
+ return NULL;
+ }
+
+ pmap[idx] = (level_alloc | PTE_VALID | PTE_USER | PTE_TABLE);
+ return PHYS_TO_VIRT(level_alloc);
+}
+
+/*
+ * Get the lowest pagemap table referring to a 4 KiB
+ * frame.
+ *
+ * @ttrb: Translation table base to use
+ * @ia: Input virtual address
+ * @alloc: If true, allocate new pagemap entries as needed
+ * @res: Result goes here
+ */
+static int
+pmap_get_tbl(paddr_t ttbrn, vaddr_t ia, bool alloc, uintptr_t **res)
+{
+ vaddr_t *root;
+ uintptr_t *l1, *l2, *l3;
+
+ root = PHYS_TO_VIRT(ttbrn);
+
+ l1 = pmap_extract(0, ia, root, alloc);
+ if (l1 == NULL) {
+ return -1;
+ }
+
+ l2 = pmap_extract(1, ia, l1, alloc);
+ if (l2 == NULL) {
+ return -1;
+ }
+
+ l3 = pmap_extract(2, ia, l2, alloc);
+ if (l3 == NULL) {
+ return -1;
+ }
+
+ *res = l3;
+ return 0;
+}
struct vas
pmap_read_vas(void)
{
- /* TODO: STUB */
struct vas vas = {0};
+
+ __ASMV(
+ "mrs %0, ttbr0_el1\n"
+ "mrs %1, ttbr1_el1\n"
+ : "=r" (vas.ttbr0_el1),
+ "=r" (vas.ttbr1_el1)
+ :
+ : "memory"
+ );
+
return vas;
}
void
pmap_switch_vas(struct vas vas)
{
- /* TODO: STUB */
+ __ASMV(
+ "msr ttbr0_el1, %0\n"
+ "msr ttbr1_el1, %1\n"
+ :
+ : "r" (vas.ttbr0_el1),
+ "r" (vas.ttbr1_el1)
+ : "memory"
+ );
return;
}
int
pmap_map(struct vas vas, vaddr_t va, paddr_t pa, vm_prot_t prot)
{
- /* TODO: STUB */
+ paddr_t ttbrn = vas.ttbr0_el1;
+ uint64_t pte_flags;
+ uintptr_t *tbl;
+ int error;
+
+ if (va >= VM_HIGHER_HALF) {
+ ttbrn = vas.ttbr1_el1;
+ }
+
+ if ((error = pmap_get_tbl(ttbrn, va, true, &tbl)) < 0) {
+ return error;
+ }
+ if (__unlikely(tbl == NULL)) {
+ return -1;
+ }
+
+ pte_flags = pmap_prot_to_pte(prot);
+ tbl[pmap_level_idx(va, 3)] = pa | pte_flags;
+ tlb_flush(va);
return 0;
}
int
pmap_unmap(struct vas vas, vaddr_t va)
{
- /* TODO: STUB */
+ paddr_t ttbrn = vas.ttbr0_el1;
+ uintptr_t *tbl;
+ int error;
+
+ if (va >= VM_HIGHER_HALF) {
+ ttbrn = vas.ttbr1_el1;
+ }
+
+ if ((error = pmap_get_tbl(ttbrn, va, true, &tbl)) < 0) {
+ return error;
+ }
+ if (__unlikely(tbl == NULL)) {
+ return -1;
+ }
+
+ tbl[pmap_level_idx(va, 3)] = 0;
+ tlb_flush(va);
return 0;
}
@@ -66,3 +305,36 @@ pmap_destroy_vas(struct vas vas)
/* TODO: STUB */
return;
}
+
+bool
+pmap_is_clean(struct vas vas, vaddr_t va)
+{
+ /* TODO: STUB */
+ return false;
+}
+
+void
+pmap_mark_clean(struct vas vas, vaddr_t va)
+{
+ /* TODO: STUB */
+ return;
+}
+
+int
+pmap_set_cache(struct vas vas, vaddr_t va, int type)
+{
+ /* TODO: STUB */
+ return 0;
+}
+
+int
+pmap_init(void)
+{
+ uint64_t mair;
+
+ mair = MT_ATTR(MT_NORMAL, MEM_NORMAL) |
+ MT_ATTR(MT_NORMAL_UC, MEM_NORMAL_UC) |
+ MT_ATTR(MT_DEVICE, MEM_DEV_NGNRNE);
+ mair_el1_write(mair);
+ return 0;
+}
diff --git a/sys/arch/aarch64/aarch64/proc_machdep.c b/sys/arch/aarch64/aarch64/proc_machdep.c
index 97902e5..cc58af9 100644
--- a/sys/arch/aarch64/aarch64/proc_machdep.c
+++ b/sys/arch/aarch64/aarch64/proc_machdep.c
@@ -37,17 +37,17 @@
* @ip: Instruction pointer.
*/
int
-md_fork(struct proc *p, struct proc *parent, uintptr_t ip)
+md_spawn(struct proc *p, struct proc *parent, uintptr_t ip)
{
/* TODO: STUB */
return 0;
}
-void
+uintptr_t
md_td_stackinit(struct proc *td, void *stack_top, struct exec_prog *prog)
{
/* TODO: STUB */
- return;
+ return 0;
}
void
diff --git a/sys/arch/aarch64/aarch64/reboot.c b/sys/arch/aarch64/aarch64/reboot.c
index 6d82133..372012a 100644
--- a/sys/arch/aarch64/aarch64/reboot.c
+++ b/sys/arch/aarch64/aarch64/reboot.c
@@ -30,9 +30,25 @@
#include <sys/reboot.h>
#include <sys/param.h>
+/*
+ * Typically the reset vector is at address 0 but this can
+ * be remapped if the vendor is feeling silly.
+ */
+void(*g_cpu_reboot)(void) = NULL;
+
void
cpu_reboot(int method)
{
- /* TODO: STUB */
+ g_cpu_reboot();
for (;;);
}
+
+/*
+ * arg0: Method bits
+ */
+scret_t
+sys_reboot(struct syscall_args *scargs)
+{
+ cpu_reboot(scargs->arg0);
+ __builtin_unreachable();
+}
diff --git a/sys/arch/aarch64/aarch64/vector.S b/sys/arch/aarch64/aarch64/vector.S
new file mode 100644
index 0000000..c8f77ca
--- /dev/null
+++ b/sys/arch/aarch64/aarch64/vector.S
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/frameasm.h>
+
+// Vector table entries are aligned at 128 bytes
+// giving us 32 exception entries
+.macro ventry label
+ .align 7
+ b \label
+.endm
+
+ .text
+x_sync_elx:
+ PUSH_XFRAME(TRAPNO_XSYNC) // Synchronous: sp+top @ X0
+ bl handle_exception // Handle the exception
+ POP_XFRAME() // Pop the trapframe
+1: hlt #0 // TODO
+ b 1b
+
+x_irq_elx:
+ PUSH_XFRAME(TRAPNO_XIRQ) // IRQ: sp+top @ X0
+ bl handle_exception // Handle the exception
+ POP_XFRAME() // Pop the trapframe
+1: hlt #0 // TODO
+ b 1b
+
+x_fiq_elx:
+ PUSH_XFRAME(TRAPNO_XFIQ) // FIQ: sp+top @ X0
+ bl handle_exception // Handle the exception
+ POP_XFRAME() // Pop the trapframe
+1: hlt #0
+ b 1b
+
+x_serr_elx:
+ PUSH_XFRAME(TRAPNO_XSERR) // SERR: sp+top @ X0
+ bl handle_exception // Handle the exception
+ POP_XFRAME() // Pop the trapframe
+1: hlt #0 // TODO
+ b 1b
+
+x_unimpl:
+1: hlt #0
+ b 1b
+
+ .align 11 // Table aligned @ 2 KiB
+ .globl __vectab
+__vectab:
+ // From current EL (w/ SP_EL0)
+ ventry x_sync_elx
+ ventry x_irq_elx
+ ventry x_fiq_elx
+ ventry x_serr_elx
+
+ // From current EL (w/ SP_ELx > 0)
+ ventry x_sync_elx
+ ventry x_irq_elx
+ ventry x_fiq_elx
+ ventry x_serr_elx
+
+ // Lower EL with faulting code in AARCH64
+ ventry x_sync_elx
+ ventry x_irq_elx
+ ventry x_fiq_elx
+ ventry x_serr_elx
+
+ ventry x_unimpl
+ ventry x_unimpl
+ ventry x_unimpl
+ ventry x_unimpl
diff --git a/sys/arch/aarch64/conf/GENERIC b/sys/arch/aarch64/conf/GENERIC
index 5691685..eeb9d9d 100644
--- a/sys/arch/aarch64/conf/GENERIC
+++ b/sys/arch/aarch64/conf/GENERIC
@@ -1,5 +1,10 @@
// Kernel options
-option SERIAL_DEBUG yes
+option SERIAL_DEBUG yes // Enable kmsg serial logging
+option USER_KMSG yes // Show kmsg in user consoles
// Kernel constants
-setval SCHED_NQUEUE 4
+setval SCHED_NQUEUE 4 // Number of scheduler queues (for MLFQ)
+
+// Console attributes
+setval CONSOLE_BG 0x000000
+setval CONSOLE_FG 0xB57614
diff --git a/sys/arch/aarch64/conf/link.ld b/sys/arch/aarch64/conf/link.ld
index c64cec3..2aa8c93 100644
--- a/sys/arch/aarch64/conf/link.ld
+++ b/sys/arch/aarch64/conf/link.ld
@@ -40,6 +40,12 @@ SECTIONS
__drivers_init_end = .;
} :rodata
+ .drivers.defer : {
+ __driversd_init_start = .;
+ *(.drivers.defer .drivers.defer)
+ __driversd_init_end = .;
+ } :rodata
+
/* Move to the next memory page for .data */
. += CONSTANT(MAXPAGESIZE);
diff --git a/sys/arch/aarch64/pci/pci_machdep.c b/sys/arch/aarch64/pci/pci_machdep.c
index fa92165..8de6cc9 100644
--- a/sys/arch/aarch64/pci/pci_machdep.c
+++ b/sys/arch/aarch64/pci/pci_machdep.c
@@ -30,20 +30,6 @@
#include <sys/types.h>
#include <dev/pci/pci.h>
-pcireg_t
-pci_readl(struct pci_device *dev, uint32_t offset)
-{
- /* TODO: STUB */
- return 0;
-}
-
-void
-pci_writel(struct pci_device *dev, uint32_t offset, pcireg_t val)
-{
- /* TODO: STUB */
- return;
-}
-
/*
* Map a BAR into kernel memory.
*
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-01 03:34:56 +0000