diff options
| -rw-r--r-- | sys/arch/amd64/lapic.c | 167 | ||||
| -rw-r--r-- | sys/arch/amd64/machdep.c | 2 | ||||
| -rw-r--r-- | sys/firmware/acpi/acpi_madt.c | 10 | ||||
| -rw-r--r-- | sys/include/arch/amd64/lapic.h | 39 | ||||
| -rw-r--r-- | sys/include/arch/amd64/lapicvar.h | 30 |
5 files changed, 246 insertions, 2 deletions
diff --git a/sys/arch/amd64/lapic.c b/sys/arch/amd64/lapic.c new file mode 100644 index 0000000..6a5ed9a --- /dev/null +++ b/sys/arch/amd64/lapic.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2023 Ian Marco Moffett and the VegaOS team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of VegaOS nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <machine/lapic.h> +#include <machine/lapicvar.h> +#include <machine/cpuid.h> +#include <machine/msr.h> +#include <sys/types.h> +#include <sys/cdefs.h> +#include <sys/syslog.h> +#include <sys/panic.h> +#include <sys/mmio.h> + +/* + * Only calls KINFO if we are the BSP. + */ +#define BSP_KINFO(...) \ + uint64_t msr_val; \ + \ + msr_val = rdmsr(IA32_APIC_BASE_MSR); \ + if (__TEST(msr_val, 1 << 8)) { \ + KINFO(__VA_ARGS__); \ + } + +__MODULE_NAME("lapic"); +__KERNEL_META("$Vega$: lapic.c, Ian Marco Moffett, " + "Local APIC driver"); + +static void *lapic_base = NULL; + +/* + * Returns true if LAPIC is supported. + * + * LAPIC is supported if CPUID.(EAX=1H):EDX[9] == 1 + */ +static inline bool +lapic_check_support(void) +{ + uint32_t eax, edx, tmp; + + __CPUID(0x00000001, eax, tmp, tmp, edx); + return __TEST(edx, 1 << 9); +} + +/* + * Reads a 32 bit value from Local APIC + * register space. + * + * @reg: Register to read from. + */ +static inline uint32_t +lapic_readl(uint32_t reg) +{ + void *addr; + + addr = (void *)((uintptr_t)lapic_base + reg); + return mmio_read32(addr); +} + +/* + * Writes a 32 bit value to Local APIC + * register space. + * + * @reg: Register to write to. + */ +static inline void +lapic_writel(uint32_t reg, uint32_t val) +{ + void *addr; + + addr = (void *)((uintptr_t)lapic_base + reg); + mmio_write32(addr, val); +} + +/* + * Set bits within a LAPIC register + * without overwriting the whole thing. + * + * @reg: Reg with bits to be set. + * @value: Value in reg will be ORd with this. + */ +static inline void +lapic_reg_set(uint32_t reg, uint32_t value) +{ + uint32_t old; + + old = lapic_readl(reg); + lapic_writel(reg, old | value); +} + +/* + * Clear bits within a LAPIC register + * without overwriting the whole thing. + * + * @reg: Reg with bits to be cleared. + * @value: Value in reg will be cleared by this value. + */ +static inline void +lapic_reg_clear(uint32_t reg, uint32_t value) +{ + uint32_t old; + + old = lapic_readl(reg); + lapic_writel(reg, old & ~(value)); +} + +void +lapic_set_base(void *mmio_base) +{ + if (lapic_base == NULL) + lapic_base = mmio_base; +} + +void +lapic_init(void) +{ + uint64_t tmp; + + /* Sanity check */ + if (lapic_base == NULL) { + panic("LAPIC base not set!\n"); + } + + if (!lapic_check_support()) { + /* + * VegaOS currently depends on the existance + * of a Local APIC. + */ + panic("This machine does not support LAPIC!\n"); + } + + /* Hardware enable the Local APIC */ + tmp = rdmsr(IA32_APIC_BASE_MSR); + wrmsr(IA32_APIC_BASE_MSR, tmp | LAPIC_HW_ENABLE); + + /* Software enable the Local APIC via SVR */ + lapic_reg_set(LAPIC_SVR, LAPIC_SW_ENABLE); + + BSP_KINFO("Enabled Local APIC for BSP\n"); + lapic_writel(LAPIC_LDR, LAPIC_STARTUP_LID); +} diff --git a/sys/arch/amd64/machdep.c b/sys/arch/amd64/machdep.c index 0b52792..e6088a0 100644 --- a/sys/arch/amd64/machdep.c +++ b/sys/arch/amd64/machdep.c @@ -33,6 +33,7 @@ #include <machine/idt.h> #include <machine/gdt.h> #include <machine/ioapic.h> +#include <machine/lapic.h> #define ISR(func) ((uintptr_t)func) #define INIT_FLAG_IOAPIC 0x00000001U @@ -71,6 +72,7 @@ processor_init(void) ioapic_init(); } + lapic_init(); /* Per core */ gdt_load(&g_gdtr); interrupts_init(); } diff --git a/sys/firmware/acpi/acpi_madt.c b/sys/firmware/acpi/acpi_madt.c index bf3007b..c23f2a4 100644 --- a/sys/firmware/acpi/acpi_madt.c +++ b/sys/firmware/acpi/acpi_madt.c @@ -30,6 +30,7 @@ #include <firmware/acpi/acpi.h> #include <firmware/acpi/tables.h> #include <machine/ioapic.h> +#include <machine/lapic.h> #include <sys/cdefs.h> #include <sys/panic.h> #include <sys/syslog.h> @@ -50,13 +51,20 @@ do_parse(void) uint8_t *cur = NULL; uint8_t *end = NULL; + void *ioapic_mmio_base = NULL; + void *lapic_mmio_base = NULL; + struct apic_header *hdr = NULL; struct ioapic *ioapic = NULL; - void *ioapic_mmio_base = NULL; cur = (uint8_t *)(madt + 1); end = (uint8_t *)madt + madt->hdr.length; + /* Init the Local APIC */ + lapic_mmio_base = (void *)(uintptr_t)madt->lapic_addr; + lapic_set_base(lapic_mmio_base); + + /* Parse the rest of the MADT */ while (cur < end) { hdr = (void *)cur; diff --git a/sys/include/arch/amd64/lapic.h b/sys/include/arch/amd64/lapic.h new file mode 100644 index 0000000..f9d5718 --- /dev/null +++ b/sys/include/arch/amd64/lapic.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2023 Ian Marco Moffett and the VegaOS team. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of VegaOS nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AMD64_LAPIC_H_ +#define _AMD64_LAPIC_H_ + +#define LAPIC_TMR_ONESHOT 0x00 +#define LAPIC_TMR_PERIODIC 0x01 + +void lapic_set_base(void *mmio_base); +void lapic_init(void); + +#endif /* !_AMD64_LAPIC_H_ */ diff --git a/sys/include/arch/amd64/lapicvar.h b/sys/include/arch/amd64/lapicvar.h index 262dec0..98b66ef 100644 --- a/sys/include/arch/amd64/lapicvar.h +++ b/sys/include/arch/amd64/lapicvar.h @@ -30,6 +30,8 @@ #ifndef _AMD64_LAPICVAR_H_ #define _AMD64_LAPICVAR_H_ +#include <sys/cdefs.h> + /* LAPIC register offsets */ #define LAPIC_ID 0x0020U /* ID Register */ #define LAPIC_VERSION 0x0030U /* Version Register */ @@ -45,8 +47,34 @@ #define LAPIC_TMR 0x0180U /* Trigger Mode Register (max=0x0220) */ #define LAPIC_IRR 0x0200U /* Interrupt Request Register (max=0x0270) */ #define LAPIC_ERR 0x0280U /* Error Status Register */ +#define LAPIC_LVT_TMR 0x0320U /* LVT Timer Register */ #define LAPIC_DCR 0x03E0U /* Divide Configuration Register (for timer) */ +#define LAPIC_INIT_CNT 0x0380U /* Initial Count Register (for timer) */ +#define LAPIC_CUR_CNT 0x0390U /* Current Count Register (for timer) */ + +#define IA32_APIC_BASE_MSR 0x1B + +/* + * To hardware enable, OR the value + * of the IA32_APIC_BASE MSR with + * LAPIC_HW_ENABLE and rewrite it. + * + * To software enable, OR the value + * of the SVR with LAPIC_SW_ENABLE + * and rewrite it. + * + * LAPIC_SW_ENABLE has the low 8 bits set + * as some hardware requires the spurious + * vector to be hardwired to 1s so we'll + * go with that to be safe. + */ +#define LAPIC_HW_ENABLE __BIT(11) +#define LAPIC_SW_ENABLE (__BIT(8) | 0xFF) + +/* The initial logical APIC ID to be set */ +#define LAPIC_STARTUP_LID 0x1 -#define IA32_APIC_BASE_MSR 0x1B +/* LVT bits */ +#define LAPIC_LVT_MASK __BIT(16) #endif /* !_AMD64_LAPICVAR_H_ */ |