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-rw-r--r--sys/arch/amd64/conf/link.ld8
-rw-r--r--sys/include/sys/cdefs.h17
-rw-r--r--sys/include/sys/param.h5
3 files changed, 29 insertions, 1 deletions
diff --git a/sys/arch/amd64/conf/link.ld b/sys/arch/amd64/conf/link.ld
index b073054..9c47a81 100644
--- a/sys/arch/amd64/conf/link.ld
+++ b/sys/arch/amd64/conf/link.ld
@@ -32,7 +32,7 @@ SECTIONS
. += CONSTANT(MAXPAGESIZE);
.data : {
- *(.data .data.*)
+ *(.data)
} :data
.bss : {
@@ -40,6 +40,12 @@ SECTIONS
*(.bss .bss.*)
} :data
+ /* -- Cache line alignment -- */
+ . = ALIGN(64);
+ .data.cacheline_aligned : {
+ *(.data.cacheline_aligned)
+ }
+
/DISCARD/ : {
*(.eh_frame)
*(.note .note.*)
diff --git a/sys/include/sys/cdefs.h b/sys/include/sys/cdefs.h
index fc21750..655a023 100644
--- a/sys/include/sys/cdefs.h
+++ b/sys/include/sys/cdefs.h
@@ -30,10 +30,27 @@
#ifndef _SYS_CDEFS_H_
#define _SYS_CDEFS_H_
+#include <sys/param.h>
+
#define __ASMV __asm__ __volatile__
#define __always_inline __attribute__((__always_inline__))
#define __packed __attribute__((__packed__))
#define __likely(exp) __builtin_expect(((exp) != 0), 1)
#define __unlikely(exp) __builtin_expect(((exp) != 0), 0)
+#if defined(_KERNEL)
+/*
+ * Align data on a cache line boundary. This is
+ * mostly useful for certain locks to ensure they
+ * have their own cache line to reduce contention.
+ *
+ */
+#ifndef __cacheline_aligned
+#define __cacheline_aligned \
+ __attribute__((__aligned__(COHERENCY_UNIT), \
+ __section__(".data.cacheline_aligned")))
+
+#endif /* __cacheline_aligned */
+#endif /* _KERNEL */
+
#endif /* !_SYS_CDEFS_H_ */
diff --git a/sys/include/sys/param.h b/sys/include/sys/param.h
index a35a094..483dc15 100644
--- a/sys/include/sys/param.h
+++ b/sys/include/sys/param.h
@@ -30,6 +30,11 @@
#ifndef _SYS_PARAM_H_
#define _SYS_PARAM_H_
+/* Assumed cache line size */
+#ifndef COHERENCY_UNIT
+#define COHERENCY_UNIT 64
+#endif
+
/* Bit related macros */
#define ISSET(v, f) ((v) & (f))
#define BIT(n) (1 << (n))