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authorsigsegv7 <ian@vegaa.systems>2023-10-18 18:22:08 -0400
committersigsegv7 <ian@vegaa.systems>2023-10-18 18:22:08 -0400
commitd42c2061e1b8abb7ddaf628b6016e7a1ad8eedb0 (patch)
treedd4839d088cb124cb9d8b082b38fcab3acbf9481 /sys
parent8775a43cf5267abba09195caf0031960d6cb2434 (diff)
kernel/amd64: lapic: Update docs
Signed-off-by: sigsegv7 <ian@vegaa.systems>
Diffstat (limited to 'sys')
-rw-r--r--sys/include/arch/amd64/lapicvar.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/sys/include/arch/amd64/lapicvar.h b/sys/include/arch/amd64/lapicvar.h
index 67cb277..6c2c37f 100644
--- a/sys/include/arch/amd64/lapicvar.h
+++ b/sys/include/arch/amd64/lapicvar.h
@@ -79,7 +79,13 @@
#define LAPIC_SW_ENABLE (__BIT(8) | 0xFF)
#define x2APIC_ENABLE_SHIFT 10
-/* The initial logical APIC ID to be set */
+/*
+ * The initial logical APIC ID to be set
+ *
+ * XXX: This value does *not* apply to processors
+ * that support x2APIC mode. In x2APIC mode
+ * the LDR register is readonly to system software.
+ */
#define LAPIC_STARTUP_LID 0x1
/* LVT bits */