diff options
| author | Ian Moffett <ian@osmora.org> | 2024-07-11 01:30:14 -0400 |
|---|---|---|
| committer | Ian Moffett <ian@osmora.org> | 2024-07-11 01:30:14 -0400 |
| commit | bf9ad82ee961b839654e2322f083c13532f2c0c6 (patch) | |
| tree | 09db2648a09e100f5027132d93e12c938a530cf9 /sys/include/dev | |
| parent | 1d258c4bfeaab845b250006ed8bf3df6776b5c11 (diff) | |
kernel/amd64: pci: Add support for PCI MSI-X
Signed-off-by: Ian Moffett <ian@osmora.org>
Diffstat (limited to 'sys/include/dev')
| -rw-r--r-- | sys/include/dev/pci/pci.h | 8 | ||||
| -rw-r--r-- | sys/include/dev/pci/pciregs.h | 5 |
2 files changed, 13 insertions, 0 deletions
diff --git a/sys/include/dev/pci/pci.h b/sys/include/dev/pci/pci.h index 3340e1a..497bfc7 100644 --- a/sys/include/dev/pci/pci.h +++ b/sys/include/dev/pci/pci.h @@ -54,6 +54,7 @@ struct pci_device { uint8_t slot; uint8_t func; + uint16_t msix_capoff; uint16_t device_id; uint16_t vendor_id; uint8_t pci_class; @@ -64,11 +65,18 @@ struct pci_device { TAILQ_ENTRY(pci_device) link; }; +struct msi_intr { + const char *name; + void(*handler)(void *); +}; + pcireg_t pci_readl(struct pci_device *dev, uint32_t offset); struct pci_device *pci_get_device(struct pci_lookup lookup, uint16_t lookup_type); int pci_map_bar(struct pci_device *dev, uint8_t barno, void **vap); void pci_writel(struct pci_device *dev, uint32_t offset, pcireg_t val); + +int pci_enable_msix(struct pci_device *dev, const struct msi_intr *intr); int pci_init(void); #endif /* !_PCI_H_ */ diff --git a/sys/include/dev/pci/pciregs.h b/sys/include/dev/pci/pciregs.h index c1b02e9..763fade 100644 --- a/sys/include/dev/pci/pciregs.h +++ b/sys/include/dev/pci/pciregs.h @@ -42,6 +42,7 @@ #define PCIREG_BAR4 0x20 /* 32 bits */ #define PCIREG_BAR5 0x24 /* 32 bits */ #define PCIREG_IRQLINE 0x3C /* 8 bits */ +#define PCIREG_CAPPTR 0x34 /* 8 bits */ #define PCIREG_CMDSTATUS 0x04 /* command (15:0), status (31:16) */ /* Macros to extract PCIREG_CLASSREV bits */ @@ -64,4 +65,8 @@ #define PCI_STATUS_CAPLIST BIT(4) #define PCI_STATUS_66MHZ BIT(5) +/* Capability IDs */ +#define PCI_CAP_MSI 0x05 +#define PCI_CAP_MSIX 0x11 + #endif /* _PCI_PCIREGS_H_ */ |