diff options
| author | sigsegv7 <ian@osmora.org> | 2023-11-12 00:16:24 -0500 |
|---|---|---|
| committer | sigsegv7 <ian@osmora.org> | 2023-11-12 00:16:24 -0500 |
| commit | f53ac3212fe8f07c99aef348e754aa8ab00081dc (patch) | |
| tree | 4f3c5ab942e900bb11e8cce4825061946d278b44 /sys/include/arch/amd64 | |
| parent | c4c3d0e5479f0415fcc21eeedcecfe745ee17dc4 (diff) | |
kernel/amd64: lapic: Remove ESR support
ESR support should be added later on; there is no need for it
as of now...
Signed-off-by: sigsegv7 <ian@osmora.org>
Diffstat (limited to 'sys/include/arch/amd64')
| -rw-r--r-- | sys/include/arch/amd64/lapicvar.h | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/sys/include/arch/amd64/lapicvar.h b/sys/include/arch/amd64/lapicvar.h index 2ad1a09..6edbeb5 100644 --- a/sys/include/arch/amd64/lapicvar.h +++ b/sys/include/arch/amd64/lapicvar.h @@ -91,10 +91,17 @@ /* LVT bits */ #define LAPIC_LVT_MASK __BIT(16) -/* Possible error bits within ESR */ -#define ESR_REDIR_IPI __BIT(4) /* Redirectible IPI */ -#define ESR_SIV __BIT(5) /* Send Illegal Vector */ -#define ESR_RIV __BIT(6) /* Received Illegal Vector */ -#define ESR_IRA __BIT(7) /* Illegal Register Address */ +/* + * Local APIC Interrupt stack [IST VALUE]. + * + * This value should be non-zero and reserved + * for only 1 interrupt vector to prevent clobbering + * of the interrupt stacks. + * + * XXX TODO: The value is correctly 0, however, this needs + * to be updated to a non-zero value as soon as + * possible. + */ +#define LAPIC_TMR_INTSTACK 0 #endif /* !_AMD64_LAPICVAR_H_ */ |