diff options
| author | sigsegv7 <ian@vegaa.systems> | 2023-10-18 18:00:49 -0400 |
|---|---|---|
| committer | sigsegv7 <ian@vegaa.systems> | 2023-10-18 18:20:16 -0400 |
| commit | 8775a43cf5267abba09195caf0031960d6cb2434 (patch) | |
| tree | a3bc0aeddb97051b355bbc488bbb405a5edf117e /sys/include/arch/amd64/lapicvar.h | |
| parent | 56a48e52c3abdba51af3178a16beff56600bc91a (diff) | |
kernel/amd64: lapic: Add basic x2APIC support
Signed-off-by: sigsegv7 <ian@vegaa.systems>
Diffstat (limited to 'sys/include/arch/amd64/lapicvar.h')
| -rw-r--r-- | sys/include/arch/amd64/lapicvar.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sys/include/arch/amd64/lapicvar.h b/sys/include/arch/amd64/lapicvar.h index 98b66ef..67cb277 100644 --- a/sys/include/arch/amd64/lapicvar.h +++ b/sys/include/arch/amd64/lapicvar.h @@ -55,6 +55,13 @@ #define IA32_APIC_BASE_MSR 0x1B /* + * The x2APIC register space is accessed via + * RDMSR/WRMSR instructions. The below defines + * the base MSR address for the register space. + */ +#define x2APIC_MSR_BASE 0x00000800 + +/* * To hardware enable, OR the value * of the IA32_APIC_BASE MSR with * LAPIC_HW_ENABLE and rewrite it. @@ -70,6 +77,7 @@ */ #define LAPIC_HW_ENABLE __BIT(11) #define LAPIC_SW_ENABLE (__BIT(8) | 0xFF) +#define x2APIC_ENABLE_SHIFT 10 /* The initial logical APIC ID to be set */ #define LAPIC_STARTUP_LID 0x1 |