kernel/aarch64: Implement initial vector stubs

Signed-off-by: Ian Moffett <ian@osmora.org>

3 files changed, 160 insertions, 7 deletions

diff --git a/sys/arch/aarch64/aarch64/locore.S b/sys/arch/aarch64/aarch64/locore.S
new file mode 100644
index 0000000..2155991
--- /dev/null
+++ b/sys/arch/aarch64/aarch64/locore.S
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+    .text
+    .globl md_cpu_init
+md_cpu_init:
+    ldr x0, =__vectab
+    msr vbar_el1, x0
+    ret
+
diff --git a/sys/arch/aarch64/aarch64/machdep.c b/sys/arch/aarch64/aarch64/machdep.c
index 2a956b8..33d7c42 100644
--- a/sys/arch/aarch64/aarch64/machdep.c
+++ b/sys/arch/aarch64/aarch64/machdep.c
@@ -34,12 +34,7 @@
 
 struct cpu_info g_bsp_ci = {0};
 
-void
-cpu_startup(struct cpu_info *ci)
-{
-    /* TODO: STUB */
-    return;
-}
+void md_cpu_init(void);
 
 void
 cpu_halt_others(void)
@@ -92,6 +87,14 @@ this_cpu(void)
 {
     struct cpu_info *ci;
 
-    __ASMV("mrs %0, tpidr_el0" : "=r" (ci));
+    __ASMV("mrs %0, tpidr_el1" : "=r" (ci));
     return ci;
 }
+
+void
+cpu_startup(struct cpu_info *ci)
+{
+    ci->self = ci;
+    __ASMV("msr tpidr_el1, %0" :: "r" (ci));
+    md_cpu_init();
+}
diff --git a/sys/arch/aarch64/aarch64/vector.S b/sys/arch/aarch64/aarch64/vector.S
new file mode 100644
index 0000000..084d54f
--- /dev/null
+++ b/sys/arch/aarch64/aarch64/vector.S
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2023-2025 Ian Marco Moffett and the Osmora Team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Hyra nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/frameasm.h>
+
+// Vector table entries are aligned at 128 bytes
+// giving us 32 exception entries
+.macro ventry label
+    .align 7
+    b \label
+.endm
+
+    .section .data
+error:
+    .ascii "got exception, halting\n\0"
+
+    .text
+x_sync_elx:
+    PUSH_XFRAME(TRAPNO_XSYNC)
+    ldr x0, =error
+    bl kprintf
+    POP_XFRAME()
+1:
+    hlt #0
+    b 1b
+
+x_irq_elx:
+    PUSH_XFRAME(TRAPNO_XSYNC)
+    ldr x0, =error
+    bl kprintf
+    POP_XFRAME()
+1:
+    hlt #0
+    b 1b
+
+.align 7
+x_fiq_elx:
+    PUSH_XFRAME(TRAPNO_XSYNC)
+    ldr x0, =error
+    bl kprintf
+    POP_XFRAME()
+1:
+    hlt #0
+    b 1b
+
+x_serr_elx:
+    PUSH_XFRAME(TRAPNO_XSYNC)
+    ldr x0, =error
+    bl kprintf
+    POP_XFRAME()
+1:
+    hlt #0
+    b 1b
+
+x_unimpl:
+    PUSH_XFRAME(TRAPNO_XSYNC)
+    ldr x0, =error
+    bl kprintf
+    POP_XFRAME()
+1:
+    hlt #0
+    b 1b
+
+    .align 11         // Table aligned @ 2 KiB
+    .globl __vectab
+__vectab:
+    // From current EL (w/ SP_EL0)
+    ventry x_sync_elx
+    ventry x_irq_elx
+    ventry x_fiq_elx
+    ventry x_serr_elx
+
+    // From current EL (w/ SP_ELx > 0)
+    ventry x_sync_elx
+    ventry x_irq_elx
+    ventry x_fiq_elx
+    ventry x_serr_elx
+
+    // Lower EL with faulting code in AARCH64
+    ventry x_sync_elx
+    ventry x_irq_elx
+    ventry x_fiq_elx
+    ventry x_serr_elx
+
+    ventry x_unimpl
+    ventry x_unimpl
+    ventry x_unimpl
+    ventry x_unimpl