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authorIan Moffett <ian@osmora.org>2025-08-13 00:06:02 -0400
committerIan Moffett <ian@osmora.org>2025-08-13 00:26:38 -0400
commit4a2bcb1575130662bcd0b8d9b698cad79c633cb5 (patch)
treeb0c9e356c087f440290388d917b423e9c9af44f6 /sys/arch
parent83372e621621cd8509adc164599b212406970576 (diff)
kernel/amd64: cpu: Add detection of invariant TSC
This commit introduces the 'CPU_FEAT_TSCINV' feature bit to indicate whether or not the CPU supports an invariant TSC. Signed-off-by: Ian Moffett <ian@osmora.org>
Diffstat (limited to 'sys/arch')
-rw-r--r--sys/arch/amd64/amd64/machdep.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/sys/arch/amd64/amd64/machdep.c b/sys/arch/amd64/amd64/machdep.c
index 6408ad3..f0571b3 100644
--- a/sys/arch/amd64/amd64/machdep.c
+++ b/sys/arch/amd64/amd64/machdep.c
@@ -306,7 +306,7 @@ cpu_get_vendor(struct cpu_info *ci)
static void
cpu_get_info(struct cpu_info *ci)
{
- uint32_t eax, ebx, ecx, unused;
+ uint32_t eax, ebx, ecx, edx;
uint8_t ext_model, ext_family;
/* Get the vendor information */
@@ -322,6 +322,14 @@ cpu_get_info(struct cpu_info *ci)
ci->feat |= CPU_FEAT_UMIP;
/*
+ * Processor power management information bits as well
+ * as bits describing RAS capabilities
+ */
+ CPUID(0x80000007, unused, unused, unused, edx);
+ if (ISSET(edx, BIT(8))
+ ci->feat |= CPU_FEAT_TSCINV;
+
+ /*
* Processor info and feature bits
*/
CPUID(0x01, eax, unused, unused, unused);