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authorsigsegv7 <ian@vegaa.systems>2023-09-14 00:22:21 -0400
committersigsegv7 <ian@vegaa.systems>2023-09-14 00:22:21 -0400
commit3a72a201448fe16657a14cfc5916b672df94acf0 (patch)
treeff0f71e02fd2791b85f7791ab6ec98a0c58bf743 /sys/arch/amd64
parentec0809d472d0f79420b7e0cebc32a01b93aeff39 (diff)
kernel/amd64: Introduce initial I/O APIC support
Signed-off-by: sigsegv7 <ian@vegaa.systems>
Diffstat (limited to 'sys/arch/amd64')
-rw-r--r--sys/arch/amd64/ioapic.c130
-rw-r--r--sys/arch/amd64/machdep.c10
2 files changed, 140 insertions, 0 deletions
diff --git a/sys/arch/amd64/ioapic.c b/sys/arch/amd64/ioapic.c
new file mode 100644
index 0000000..70a9114
--- /dev/null
+++ b/sys/arch/amd64/ioapic.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2023 Ian Marco Moffett and the VegaOS team.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of VegaOS nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/ioapic.h>
+#include <machine/ioapicvar.h>
+#include <sys/panic.h>
+#include <sys/mmio.h>
+#include <sys/cdefs.h>
+#include <sys/syslog.h>
+
+__MODULE_NAME("ioapic");
+__KERNEL_META("$Vega$: ioapic.c, Ian Marco Moffett, "
+ "I/O APIC driver");
+
+#define IOAPIC_BASE_OFF(off) ((void *)((uintptr_t)ioapic_base + off))
+
+static void *ioapic_base = NULL;
+
+/*
+ * Reads a 32 bit value from the IOAPIC
+ * register space.
+ *
+ * @reg: Register to read from.
+ */
+static uint32_t
+ioapic_readl(uint16_t reg)
+{
+ mmio_write32(IOAPIC_BASE_OFF(IOREGSEL), reg);
+ return mmio_read32(IOAPIC_BASE_OFF(IOWIN));
+}
+
+/*
+ * Writes a 32 bit value to the IOAPIC
+ * register space.
+ *
+ * @reg: Register to write to.
+ * @val: Value to write.
+ */
+static void
+ioapic_writel(uint16_t reg, uint32_t val)
+{
+ mmio_write32(IOAPIC_BASE_OFF(IOREGSEL), reg);
+ mmio_write32(IOAPIC_BASE_OFF(IOWIN), val);
+}
+
+/*
+ * Reads an I/O APIC redirection entry.
+ *
+ * @entry: Entry variable to read into.
+ * @index: Index to read.
+ */
+static void
+ioapic_read_redentry(union ioapic_redentry *entry, uint8_t index)
+{
+ uint32_t lo, hi;
+
+ lo = ioapic_readl(IOREDTBL + index * 2);
+ hi = ioapic_readl(IOREDTBL + index * 2 + 1);
+
+ entry->value = ((uint64_t)hi << 32) | lo;
+}
+
+/*
+ * Writes an I/O APIC redirection entry.
+ *
+ * @entry: Entry variable to write.
+ * @index: Index to write to.
+ */
+static void
+ioapic_write_redentry(const union ioapic_redentry *entry, uint8_t index)
+{
+ ioapic_writel(IOREDTBL + index * 2, (uint32_t)entry->value);
+ ioapic_writel(IOREDTBL + index * 2 + 1, (uint32_t)(entry->value >> 32));
+}
+
+void
+ioapic_set_base(void *mmio_base)
+{
+ if (ioapic_base == NULL)
+ ioapic_base = mmio_base;
+}
+
+void
+ioapic_init(void)
+{
+ size_t tmp;
+ uint8_t redir_entry_cnt;
+ union ioapic_redentry redir_entry;
+
+ /* Sanity check */
+ if (ioapic_base == NULL)
+ panic("ioapic base not set!\n");
+
+ tmp = ioapic_readl(IOAPICVER);
+ redir_entry_cnt = __SHIFTOUT(tmp, 0xFF << 16) + 1;
+
+ KINFO("Masking %d GSIs...\n", redir_entry_cnt);
+
+ for (uint8_t i = 0; i < redir_entry_cnt; ++i) {
+ ioapic_read_redentry(&redir_entry, i);
+ redir_entry.interrupt_mask = 1;
+ ioapic_write_redentry(&redir_entry, i);
+ }
+}
diff --git a/sys/arch/amd64/machdep.c b/sys/arch/amd64/machdep.c
index 4da73ae..0b52792 100644
--- a/sys/arch/amd64/machdep.c
+++ b/sys/arch/amd64/machdep.c
@@ -32,8 +32,10 @@
#include <machine/trap.h>
#include <machine/idt.h>
#include <machine/gdt.h>
+#include <machine/ioapic.h>
#define ISR(func) ((uintptr_t)func)
+#define INIT_FLAG_IOAPIC 0x00000001U
static void
interrupts_init(void)
@@ -61,6 +63,14 @@ processor_halt(void)
void
processor_init(void)
{
+ /* Indicates what doesn't need to be init anymore */
+ static uint8_t init_flags = 0;
+
+ if (!__TEST(init_flags, INIT_FLAG_IOAPIC)) {
+ init_flags |= INIT_FLAG_IOAPIC;
+ ioapic_init();
+ }
+
gdt_load(&g_gdtr);
interrupts_init();
}