kernel/amd64: lapic: Remove ESR support

ESR support should be added later on; there is no need for it
as of now...

Signed-off-by: sigsegv7 <ian@osmora.org>

2 files changed, 12 insertions, 26 deletions

diff --git a/sys/arch/amd64/lapic.c b/sys/arch/amd64/lapic.c
index 6f2f6c1..af219d2 100644
--- a/sys/arch/amd64/lapic.c
+++ b/sys/arch/amd64/lapic.c
@@ -208,27 +208,6 @@ lapic_set_ldr(void)
         lapic_writel(LAPIC_LDR, LAPIC_STARTUP_LID);
 }
 
-/*
- * Reads the Local APIC error status
- * register. Returns the value read.
- *
- * XXX: It is a good idea to save the value returned as
- *      each read will clear the register.
- */
-static inline uint32_t
-lapic_read_esr(void)
-{
-    /*
-     * We'll need to write 0 to clear the ESR and reload
-     * it with any new errors that happened... In xAPIC mode
-     * we can write anything to do this; however, in x2APIC
-     * mode, writes of 0 are enforced. We'll only write 0 to
-     * work both with x2APIC and xAPIC mode...
-     */
-    lapic_writel(LAPIC_ERR, 0);
-    return lapic_readl(LAPIC_ERR);
-}
-
 void
 lapic_timer_init(size_t *freq_out)
 {
diff --git a/sys/include/arch/amd64/lapicvar.h b/sys/include/arch/amd64/lapicvar.h
index 2ad1a09..6edbeb5 100644
--- a/sys/include/arch/amd64/lapicvar.h
+++ b/sys/include/arch/amd64/lapicvar.h
@@ -91,10 +91,17 @@
 /* LVT bits */
 #define LAPIC_LVT_MASK            __BIT(16)
 
-/* Possible error bits within ESR */
-#define ESR_REDIR_IPI   __BIT(4)        /* Redirectible IPI */
-#define ESR_SIV         __BIT(5)        /* Send Illegal Vector */
-#define ESR_RIV         __BIT(6)        /* Received Illegal Vector */
-#define ESR_IRA         __BIT(7)        /* Illegal Register Address */
+/*
+ * Local APIC Interrupt stack [IST VALUE].
+ *
+ * This value should be non-zero and reserved
+ * for only 1 interrupt vector to prevent clobbering
+ * of the interrupt stacks.
+ *
+ * XXX TODO: The value is correctly 0, however, this needs
+ *           to be updated to a non-zero value as soon as
+ *           possible.
+ */
+#define LAPIC_TMR_INTSTACK  0
 
 #endif  /* !_AMD64_LAPICVAR_H_ */